公开(公告)号：US20240395815A1

公开(公告)日：2024-11-28

申请号：US18200967

申请日：2023-05-23

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Manish CHANDHOK ,  Tsuan-Chung CHANG ,  Robert JOACHIM ,  Peter NGUYEN ,  Lily MAO ,  Erik SKIBINSKI

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Integrated circuit structures having metal-containing fin isolation regions are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure. A dielectric gate cut plug is in the gate cut. The dielectric gate plug includes a metal-containing dielectric material.