公开(公告)号：US20160179375A1

公开(公告)日：2016-06-23

申请号：US14580125

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： SCOTT W. KIRVAN ,  ANDY M. RUDOFF ,  MAHESH S. NATU ,  Murugasamy K. NACHIMUTHU

IPC: G06F3/06 ,  G11C14/00

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/2542 ,  G06F2212/7204 ,  G11C5/04 ,  Y02D10/13

Abstract: Methods and apparatus to allocating and/or configuring persistent memory are described. In an embodiment, memory controller logic configures non-volatile memory into a plurality of partitions at least in part based on one or more attributes. One or more volumes (visible to an application or operating system) are formed from one or more of the plurality of partitions. Each of the one or more volumes includes one or more of the plurality of partitions having at least one similar attribute from the one or more attributes. In another embodiment, memory controller logic configures a Non-Volatile Memory (NVM) Dual Inline Memory Module (DIMM) into a persistent region and a volatile region. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了分配和/或配置持久存储器的方法和装置。 在一个实施例中，存储器控制器逻辑至少部分地基于一个或多个属性将非易失性存储器配置成多个分区。 一个或多个卷（对应用或操作系统可见）由多个分区中的一个或多个形成。 所述一个或多个卷中的每一个包括所述多个分区中的一个或多个具有来自所述一个或多个属性的至少一个相似属性。 在另一个实施例中，存储器控制器逻辑将非易失性存储器（NVM）双列直插存储器模块（DIMM）配置为持久区域和易失性区域。 还公开并要求保护其他实施例。

公开(公告)号：US20170371689A1

公开(公告)日：2017-12-28

申请号：US15665382

申请日：2017-07-31

Applicant: INTEL CORPORATION

Inventor： MAHESH S. NATU ,  SHAMANNA M. DATTA

IPC: G06F9/455 ,  G06F21/57 ,  G06F11/30 ,  G06F21/53

Abstract: Various embodiments are generally directed to the provision and use of various hardware and software components of a computing device to monitor the state of layered virtual machine (VM) monitoring software components. An apparatus includes a first processor element; and logic to receive an indication that a first timer has reached an end of a first period of time, monitor execution of a VMM (virtual machine monitor) watcher by a second processor element, determine whether the second processor element completes execution of the VMM watcher to verify integrity of a VMM before a second timer reaches an end of a second period of time, and transmit an indication of the determination to a computing device. Other embodiments are described and claimed.