公开(公告)号：US20170242694A1

公开(公告)日：2017-08-24

申请号：US15445741

申请日：2017-02-28

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  MOSTAFA HAGOG ,  ROBERT VALENTINE ,  AMIT GRADSTEIN ,  SIMON RUBANOVICH ,  ZEEV SPERBER

IPC: G06F9/30 ,  G06F7/544

CPC classification number: G06F9/3001 ,  G06F7/50 ,  G06F7/544 ,  G06F9/30036 ,  G06F9/3836 ,  G06F9/3877 ,  G06F15/78 ,  G06F2207/5442

Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.