公开(公告)号：US09195606B2

公开(公告)日：2015-11-24

申请号：US13976248

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Ragavendra Natarajan ,  Jayesh Guar ,  Nithiyanandan Bashyam ,  Mainak Chaudhuri ,  Sreenivas Subramoney

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/14 ,  G06F12/12

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/126 ,  G06F12/128 ,  G06F13/14 ,  G06F2212/62

Abstract: A cache memory eviction method includes maintaining thread-aware cache access data per cache block in a cache memory, wherein the cache access data is indicative of a number of times a cache block is accessed by a first thread, associating a cache block with one of a plurality of bins based on cache access data values of the cache block, and selecting a cache block to evict from a plurality of cache block candidates based, at least in part, upon the bins with which the cache block candidates are associated.

Abstract translation: 高速缓存存储器驱逐方法包括：将每个高速缓存块的线程感知高速缓存访​​问数据保存在高速缓冲存储器中，其中高速缓存访​​问数据指示高速缓存块被第一线程访问的次数，将高速缓存块与 基于高速缓存块的高速缓存访​​问数据值的多个仓，并且至少部分地基于与高速缓存块候选相关联的区间，从多个高速缓存块候选中选择高速缓存块。

公开(公告)号：US20140351524A1

公开(公告)日：2014-11-27

申请号：US13976248

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Ragavendra Natarajan ,  Jayesh Guar ,  Nithiyanandan Bashyam ,  Mainak Chaudhuri ,  Sreenivas Subramoney

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/126 ,  G06F12/128 ,  G06F13/14 ,  G06F2212/62

Abstract: A cache memory eviction method includes maintaining thread-aware cache access data per cache block in a cache memory, wherein the cache access data is indicative of a number of times a cache block is accessed by a first thread, associating a cache block with one of a plurality of bins based on cache access data values of the cache block, and selecting a cache block to evict from a plurality of cache block candidates based, at least in part, upon the bins with which the cache block candidates are associated.

Abstract translation: 高速缓存存储器驱逐方法包括：将每个高速缓存块的线程感知高速缓存访​​问数据保存在高速缓冲存储器中，其中高速缓存访​​问数据指示高速缓存块被第一线程访问的次数，将高速缓存块与 基于高速缓存块的高速缓存访​​问数据值的多个仓，并且至少部分地基于与高速缓存块候选相关联的区间，从多个高速缓存块候选中选择高速缓存块。

公开(公告)号：US20190286567A1

公开(公告)日：2019-09-19

申请号：US15923174

申请日：2018-03-16

Applicant: Intel Corporation

Inventor： Mainak Chaudhuri ,  Jayesh Gaur ,  Sreenivas Subramoney ,  Hong Wang

IPC: G06F12/0895 ,  G06F12/0891 ,  G06F12/0804 ,  G06F12/12

Abstract: In one embodiment, a processor includes: a cache memory to store a plurality of cache lines; and a cache controller to control the cache memory. The cache controller may include a control circuit to allocate a virtual write buffer within the cache memory in response to a bandwidth on an interconnect that exceeds a first bandwidth threshold. The cache controller may further include a replacement circuit to control eviction of cache lines from the cache memory. Other embodiments are described and claimed.

公开(公告)号：US10013352B2

公开(公告)日：2018-07-03

申请号：US14498963

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Sreenivas Subramoney ,  Jayesh Gaur ,  Mukesh Agrawal ,  Mainak Chaudhuri

IPC: G06F12/12 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0842 ,  G06F12/123

CPC classification number: G06F12/0811 ,  G06F12/0813 ,  G06F12/0842 ,  G06F12/123 ,  G06F2212/1024 ,  G06F2212/1056 ,  G06F2212/3042

Abstract: Embodiments described include systems, apparatuses, and methods using sectored dynamic random access memory (DRAM) cache. An exemplary apparatus may include at least one hardware processor core and a sectored dynamic random access (DRAM) cache coupled to the at least one hardware processor core.