公开(公告)号：US10013352B2

公开(公告)日：2018-07-03

申请号：US14498963

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Sreenivas Subramoney ,  Jayesh Gaur ,  Mukesh Agrawal ,  Mainak Chaudhuri

IPC: G06F12/12 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0842 ,  G06F12/123

CPC classification number: G06F12/0811 ,  G06F12/0813 ,  G06F12/0842 ,  G06F12/123 ,  G06F2212/1024 ,  G06F2212/1056 ,  G06F2212/3042

Abstract: Embodiments described include systems, apparatuses, and methods using sectored dynamic random access memory (DRAM) cache. An exemplary apparatus may include at least one hardware processor core and a sectored dynamic random access (DRAM) cache coupled to the at least one hardware processor core.