公开(公告)号：US12068904B2

公开(公告)日：2024-08-20

申请号：US17131823

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Marc Jan Georges Tiebout

IPC: H04L27/38 ,  H03D3/00 ,  H04B1/04 ,  H04L27/36

CPC classification number: H04L27/3863 ,  H03D3/009 ,  H04B1/0475 ,  H04L27/364

Abstract: An apparatus and method for in-phase/quadrature (I/Q) imbalance correction in a transceiver. The apparatus includes an I/Q imbalance correction circuit and a correction coefficient generation circuit. The I/Q imbalance correction circuit is configured to modify I/Q data in a frequency domain using correction coefficients to generate corrected I/Q data. The correction coefficient generation circuit is configured to generate the correction coefficients for the I/Q imbalance correction circuit based on the I/Q data and reference data.

公开(公告)号：US12273074B2

公开(公告)日：2025-04-08

申请号：US17358042

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Marc Jan Georges Tiebout ,  Ramon Sanchez ,  Hazar Yuksel

IPC: H03F1/32 ,  H03F3/21

Abstract: A system and method for digital correction for a dynamically varying non-linear system. The system includes a correction circuitry including at least one look-up table (LUT). The correction circuitry is configured to receive an input signal and modify the input signal to be processed by the non-linear system using at least one LUT to correct non-linearity incurred by the non-linear system. The at least one LUT is addressed by a magnitude or power of the input signal and a dynamically varying parameter associated with the input signal. The dynamically varying parameter may be one of average signal power of the input signal, a differential of the average power of the input signal, a directional beam index, or temperature.

公开(公告)号：US12261637B2

公开(公告)日：2025-03-25

申请号：US17358040

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Marc Jan Georges Tiebout

IPC: H04B1/04 ,  H04L5/12 ,  H04L25/06

Abstract: A method and apparatus for cancelling local oscillator feedthrough (LOFT). A transmitter includes a first mixer configured to mix a transmit signal with a first local oscillator signal. An observation receiver receives a fraction of a power of the transmit signal as a feedback signal and processes the feedback signal. The observation receiver includes a second mixer configured to mix the feedback signal with a second local oscillator signal. A LOFT correction estimation circuitry is configured to determine a DC offset to cancel LOFT at the first mixer in the transmitter based on measurements on outputs of the second mixer. An LOFT correction circuitry is configured to add the DC offset to the transmit signal. The LOFT correction estimation circuitry may determine the DC offset based on several measurements obtained by varying the DC offset and a phase shift in the second local oscillator signal in the observation receiver.

公开(公告)号：US12170526B2

公开(公告)日：2024-12-17

申请号：US18054628

申请日：2022-11-11

Applicant: Intel Corporation

Inventor： Daniel Gruber ,  Kameran Azadet ,  Martin Clara ,  Marc Jan Georges Tiebout

IPC: H03M1/66 ,  H03D7/16 ,  H04B1/00 ,  H04B1/04

Abstract: A semiconductor device comprising at least one transmit path is provided. The transmit path comprises an input node for receiving a digital baseband signal. Further, the transmit path comprises digital mixer circuitry coupled to the input node and configured to generate an upconverted digital baseband signal by upconverting a frequency of the digital baseband signal. Additionally, the transmit path comprises Digital-to-Analog Converter (DAC) circuitry coupled to the digital mixer circuitry and configured to generate an analog radio frequency signal based on the upconverted digital baseband signal. The transmit path comprises first analog mixer circuitry coupleable to an output of the DAC circuitry, and second analog mixer circuitry coupleable to the output of the DAC circuitry. Further, the transmit path comprises a first output node coupleable to an output of the first analog mixer circuitry, and a second output node coupleable to an output of the second analog mixer circuitry.

公开(公告)号：US12057871B2

公开(公告)日：2024-08-06

申请号：US18062030

申请日：2022-12-06

Applicant: Intel Corporation

Inventor： Marc Jan Georges Tiebout ,  Hazar Yuksel ,  Kameran Azadet

IPC: H04B1/04 ,  H04W16/28

CPC classification number: H04B1/0475 ,  H04W16/28 ,  H04B2001/0425

Abstract: A wireless communication system including a phased array comprising a plurality of antennas configured to emit a respective radio wave based on a respective antenna signal. Further, the system includes a plurality of power amplifiers each coupled to one of the plurality of antennas via a feed line and configured to output the antenna signal to the feed line. Also, the system includes a plurality of directional couplers each coupled into one of the feed lines and comprising a third port configured to output a fraction of a power received at a first port coupled to the power amplifier via the feed line, likewise a fourth port configured to output a fraction of a power received at a second port. Additionally, the system includes switching circuitry configured to alternately couple the third port to a first feedback receiver, and to alternately couple the fourth port to a second feedback receiver.