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公开(公告)号：US12206426B2
公开(公告)日：2025-01-21
申请号：US17358044
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Albert Molina , Martin Clara , Kameran Azadet
Abstract: A system and method for equalization of a linear or non-linear system. The system includes an adder configured to add an analog reference signal and an input signal, a processing system configured to process a sum of the analog reference signal and the input signal, a non-linear equalizer (NLEQ) configured to process an output of the processing system to remove a distortion incurred by the processing system, a calibration circuitry configured to generate a reconstructed reference signal in digital domain based on measurement of the analog reference signal, and generate coefficients for the NLEQ based on the reconstructed reference signal and the output of the processing system, and a subtractor configured to subtract the reconstructed reference signal from an output of the NLEQ. The analog reference signal may be a sinusoid including single or multiple tones of sinusoids. The non-linear system may be an analog-to-digital converter (ADC).
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公开(公告)号：US11962320B2
公开(公告)日：2024-04-16
申请号：US17753917
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Kameran Azadet , Martin Clara , Daniel Gruber , Albert Molina , Hundo Shin
CPC classification number: H03M1/1071 , G01R31/2856 , G01R31/3187 , G01R31/26 , H03M1/0854 , H03M1/462
Abstract: A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.
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公开(公告)号：US20210409065A1
公开(公告)日：2021-12-30
申请号：US16912741
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： Daniel Gruber , L. Mark Elzinga , Martin Clara
Abstract: The present disclosure relates to a concept for a transformer, a transmitter circuit, a semiconductor chip, a semiconductor package, a base station, a mobile device and a method for a radio frequency transmitter. The transformer for a radio frequency transmitter circuit comprises a primary coil and a secondary coils, which are configured to receive an input signal and to provide an output signal, and a ternary coil configured to provide a feedback signal.
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公开(公告)号：US20210409015A1
公开(公告)日：2021-12-30
申请号：US16912800
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： Giacomo Cascio , Martin Clara , Christian Lindholm
IPC: H03K17/041 , H03M1/12 , G11C27/02 , H03F3/45 , H04B1/40
Abstract: The present disclosure relates to a bootstrapped switch circuit, a track-and-hold circuit, an analog-to-digital converter, a method for operating a track-and-hold circuit, a base station, and a mobile station. The bootstrapped switch circuit comprises an output for an output signal, a first input, a switching element configured to couple the output with a signal from the first input, a bootstrapper capacitor configured to drive the switching element, and a second input coupled to the bootstrapper capacitor.
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公开(公告)号：US11171663B2
公开(公告)日：2021-11-09
申请号：US16833729
申请日：2020-03-30
Applicant: Intel Corporation
Inventor： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.
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Patent Agency Ranking
公开(公告)号：US10715185B1
公开(公告)日：2020-07-14
申请号：US16369317
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
Abstract: A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.
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公开(公告)号：US10608661B1
公开(公告)日：2020-03-31
申请号：US16369262
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.
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公开(公告)号：US12278649B2
公开(公告)日：2025-04-15
申请号：US17358131
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Ramon Sanchez , Kameran Azadet , Martin Clara , Daniel Gruber
Abstract: A processing device is provided. The processing device comprises one or more interfaces configured to transmit information to a nonlinear device and processing circuitry configured to control the one or more interfaces and to. Further, the processing circuitry is configured to transmit an excitation signal to the nonlinear device and to receive response information from the nonlinear device. Further, the processing circuitry is configured to determine a linear response of the nonlinear device based on the response information and to determine a nonlinear response of the nonlinear device based on the determined linear response.
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公开(公告)号：US12170526B2
公开(公告)日：2024-12-17
申请号：US18054628
申请日：2022-11-11
Applicant: Intel Corporation
Inventor： Daniel Gruber , Kameran Azadet , Martin Clara , Marc Jan Georges Tiebout
Abstract: A semiconductor device comprising at least one transmit path is provided. The transmit path comprises an input node for receiving a digital baseband signal. Further, the transmit path comprises digital mixer circuitry coupled to the input node and configured to generate an upconverted digital baseband signal by upconverting a frequency of the digital baseband signal. Additionally, the transmit path comprises Digital-to-Analog Converter (DAC) circuitry coupled to the digital mixer circuitry and configured to generate an analog radio frequency signal based on the upconverted digital baseband signal. The transmit path comprises first analog mixer circuitry coupleable to an output of the DAC circuitry, and second analog mixer circuitry coupleable to the output of the DAC circuitry. Further, the transmit path comprises a first output node coupleable to an output of the first analog mixer circuitry, and a second output node coupleable to an output of the second analog mixer circuitry.
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公开(公告)号：US12143073B2
公开(公告)日：2024-11-12
申请号：US17131962
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Martin Clara , Giacomo Cascio
Abstract: A signal envelope detector is provided. The signal envelope detector includes an input node configured to receive an input signal. Further, the signal envelope detector includes a capacitive voltage divider coupled to the input node and configured to generate an attenuated input signal by voltage division of the input signal. The signal envelope detector additionally includes a source follower transistor coupled between a first node configured to receive a first voltage supply signal and a second node configured to receive a second voltage supply signal. A gate terminal of the source follower transistor is coupled to the capacitive voltage divider and configured to receive the attenuated input signal. The signal envelope detector includes a rectifier circuit configured to receive and rectify an output signal of the source follower transistor. In addition, the signal envelope detector includes a low-pass filter coupled to the rectifier circuit and configured to generate an envelope signal indicative of a rectified envelope of the input signal by low-pass filtering of an output signal of the rectifier circuit.
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