公开(公告)号：US20240134804A1

公开(公告)日：2024-04-25

申请号：US17968989

申请日：2022-10-18

Applicant: Intel Corporation

Inventor： Marcin Andrzej Chrapek ,  Reshma Lal

IPC: G06F12/1027 ,  G06F12/0882 ,  G06F12/14

CPC classification number: G06F12/1027 ,  G06F12/0882 ,  G06F12/1408

Abstract: An apparatus comprising translator circuitry to receive a plurality of physical addresses of memory data, determine an offset associated with each of the physical page addresses and apply a tweak seed to each offset to generate a plurality of tweaks.

公开(公告)号：US20240305465A1

公开(公告)日：2024-09-12

申请号：US18665188

申请日：2024-05-15

Applicant: Intel Corporation

Inventor： Anjo Lucas Vahldiek-Oberwagner ,  Marcin Andrzej Chrapek ,  Scott Constable

IPC: H04L9/32

CPC classification number: H04L9/3236

Abstract: Systems, apparatus, methods, and articles of manufacture to validate the accuracy of artificial intelligence models are disclosed. An example apparatus includes machine-readable instructions; and at least one processor circuit to be programmed by the machine-readable instructions to: compute accuracy statistics of an artificial intelligence model using software applied by a trusted third party and an input data set; determine a signed artifact based on (1) the accuracy statistics indicative of the accuracy of the artificial intelligence model, (2) the software applied by the trusted third party, and (3) the input data set; and communicate the signed artifact to a user of the artificial intelligence model.

公开(公告)号：US20240160581A1

公开(公告)日：2024-05-16

申请号：US17986528

申请日：2022-11-14

Applicant: Intel Corporation

Inventor： Marcin Andrzej Chrapek ,  Reshma Lal

IPC: G06F12/14 ,  G06F12/0842

CPC classification number: G06F12/1408 ,  G06F12/0842

Abstract: An apparatus includes a central processing unit (CPU), including a plurality of processing cores, each having a cache memory, a fabric interconnect coupled to the plurality of processing cores and cryptographic circuitry, coupled to the fabric interconnect including mesh stop station to receive memory data and determine a destination of the memory data and encryption circuitry to encrypt/decrypt the memory data based on a destination of the memory data.

公开(公告)号：US20240330466A1

公开(公告)日：2024-10-03

申请号：US18676413

申请日：2024-05-28

Applicant: Intel Corporation

Inventor： Scott Douglas Constable ,  Marcin Andrzej Chrapek ,  Marcin Spoczynski ,  Cory Cornelius ,  Mona Vij ,  Anjo Lucas Vahldiek-Oberwagner

IPC: G06F21/57

CPC classification number: G06F21/57

Abstract: Methods, apparatus, systems, and articles of manufacture to verify integrity of a model are disclosed. An example apparatus includes programmable circuitry to initialize an instance of a trusted execution environment; upload a security manifest of the trusted execution environment and a machine learning model; determine whether to store the machine learning model into a memory based on checking of the security manifest; determine whether the machine learning model is valid; and output a validation result.

公开(公告)号：US20240232097A9

公开(公告)日：2024-07-11

申请号：US17968989

申请日：2022-10-19

Applicant: Intel Corporation

Inventor： Marcin Andrzej Chrapek ,  Reshma Lal

IPC: G06F12/1027 ,  G06F12/0882 ,  G06F12/14

CPC classification number: G06F12/1027 ,  G06F12/0882 ,  G06F12/1408

Abstract: An apparatus comprising translator circuitry to receive a plurality of physical addresses of memory data, determine an offset associated with each of the physical page addresses and apply a tweak seed to each offset to generate a plurality of tweaks.