PROVIDING REDUCED LATENCY CREDIT INFORMATION IN A PROCESSOR

    公开(公告)号:US20180157287A1

    公开(公告)日:2018-06-07

    申请号:US15370207

    申请日:2016-12-06

    CPC classification number: G06F1/12 G06F1/32 G06F1/3243

    Abstract: In one embodiment, a processor includes a credit circuit to communicate credit information between a first clock domain of the processor and a second clock domain of the processor. The credit circuit may include: a loopback path to communicate the credit information between the first clock domain and the second clock domain; and a bypass path to cause the credit information to traverse only a portion of the loopback path, based at least in part on a state of the second clock domain. Other embodiments are described and claimed.

    Providing reduced latency credit information in a processor

    公开(公告)号:US10198027B2

    公开(公告)日:2019-02-05

    申请号:US15370207

    申请日:2016-12-06

    Abstract: In one embodiment, a processor includes a credit circuit to communicate credit information between a first clock domain of the processor and a second clock domain of the processor. The credit circuit may include: a loopback path to communicate the credit information between the first clock domain and the second clock domain; and a bypass path to cause the credit information to traverse only a portion of the loopback path, based at least in part on a state of the second clock domain. Other embodiments are described and claimed.

Patent Agency Ranking