公开(公告)号：US20180331034A1

公开(公告)日：2018-11-15

申请号：US16045369

申请日：2018-07-25

Applicant: Intel Corporation

Inventor： Deepak THIMMEGOWDA ,  Aaron YIP ,  Mark HELM ,  Yongna LI

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11578

Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.

公开(公告)号：US20170287833A1

公开(公告)日：2017-10-05

申请号：US15085151

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Deepak THIMMEGOWDA ,  Aaron YIP ,  Mark HELM ,  Yongna LI

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11578 ,  H01L28/00

Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.