公开(公告)号：US09837499B2

公开(公告)日：2017-12-05

申请号：US15326022

申请日：2014-08-13

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Seung Hoon Sung ,  Sanaz Gardner ,  Marko Radosavlijevic ,  Robert Chau

IPC: H01L29/15 ,  H01L29/417 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41783 ,  H01L21/28587 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Techniques related to III-N transistors having self aligned gates, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a polarization layer between a raised source and a raised drain, a gate between the source and drain and over the polarization layer, and lateral epitaxial overgrowths over the source and drain and having and opening therebetween such that at least a portion of the gate adjacent to the polarization layer is aligned with the opening.