公开(公告)号：US20200210172A1

公开(公告)日：2020-07-02

申请号：US16233650

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Michael ESPIG ,  Matthew C. MERTEN ,  Sean MIRKES

IPC: G06F9/22 ,  G06F9/445 ,  G06F9/54

Abstract: A system for processing data flow array instructions is described. The system includes a data flow array, which includes a plurality of processing elements; a decoder to receive a data flow array instruction and generate a set of microinstructions based on the data flow array instruction; a reservation station to receive and dispatch each microinstruction in the set of microinstructions, wherein the set of microinstructions includes a configuration microinstruction for configuring the data flow array for processing the data flow array instruction; a configuration watcher to receive the configuration microinstruction and to add a configuration identifier and a set of parameters of the configuration microinstruction to a configuration queue for the data flow array, wherein the data flow array is to configure the plurality of processing elements based on configuration information associated with the configuration identifier and the set of parameters.

公开(公告)号：US20200210320A1

公开(公告)日：2020-07-02

申请号：US16235489

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Beeman STRONG ,  Matthew C. MERTEN ,  Jason AGRON

IPC: G06F11/36

Abstract: A method for tracing software code executing on a core of a processor is described. The method includes generating a set of packets for a trace packet stream based on a main cycle counter, which maintains a count of cycles elapsing in the core since a packet was emitted into the trace packet stream, and a commit cycle counter, which maintains a cycle count in the core since the last commit operation, wherein the generating comprises (1) storing a value of the main cycle counter in the commit cycle counter in response to detecting a commit operation and (2) storing a value of the commit cycle counter in the main cycle counter in response to detecting an abort in the core; and emitting the set of packets from the processor into the trace packet stream for tracing execution of the software code.

公开(公告)号：US20170024213A1

公开(公告)日：2017-01-26

申请号：US15159040

申请日：2016-05-19

Applicant: Intel Corporation

Inventor： Bambang SUTANTO ,  Srikanth T. SRINIVASAN ,  Matthew C. MERTEN ,  Chia Yin Kevin LAI ,  Ammon J. CHRISTIANSEN ,  Justin M. DEINLEIN

IPC: G06F9/38

CPC classification number: G06F9/384 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/4881

Abstract: A processor and method are described for scheduling operations for execution within a reservation station. For example, a method in accordance with one embodiment of the invention includes the operations of: classifying a plurality of operations based on the execution ports usable to execute those operations; allocating the plurality of operations into groups within a reservation station based on the classification, wherein each group is serviced by one or more execution ports corresponding to the classification, and wherein two or more entries within a group share a common read port and a common write port; dynamically scheduling two or more operations in a group for concurrent execution based on the ports capable of executing those operations and a relative age of the operations.

Abstract translation: 描述了用于在保留站内执行的调度操作的处理器和方法。 例如，根据本发明的一个实施例的方法包括以下操作：基于可用于执行这些操作的执行端口对多个操作进行分类; 基于分类，将多个操作分配到保留站内的组中，其中每个组由对应于分类的一个或多个执行端口服务，并且其中组内的两个或多个条目共享公共读取端口和公共写入 港口; 基于能够执行这些操作的端口和操作的相对年龄，动态地调度用于并发执行的组中的两个或更多个操作。