公开(公告)号：US20220308980A1

公开(公告)日：2022-09-29

申请号：US17834211

申请日：2022-06-07

Applicant: Intel Corporation

Inventor： Michael LEMAY ,  Beeman STRONG

IPC: G06F11/34 ,  G06F11/30 ,  G06F21/57 ,  G06F21/56

Abstract: Processor trace systems and methods are described. For example, one embodiment comprises executing instrumented code by a compiler, the instrumented code including at least one call to un-instrumented code. The compiler can determine the at least one call to un-instrumented code is a next call to be executed. A resume tracing instruction can be inserted into the instrumented code prior to the at least one call to the un-instrumented code. The resume tracing instruction can be executed to selectively add processor tracing to the at least one call to the un-instrumented code, and the at least one call to the un-instrumented code can be executed.

公开(公告)号：US20250004871A1

公开(公告)日：2025-01-02

申请号：US18217501

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Beeman STRONG ,  Stanislav BRATANOV ,  Markus METZGER ,  Jason W. BRANDT ,  Stalinselvaraj JEYASINGH

IPC: G06F11/07

Abstract: Apparatus and method for a processor trace trigger tracing. A processor, comprising: a plurality of processing cores configurable as a plurality of logical processors; processor trace circuitry to perform trace operations to capture and process information related to program code executed by one or more of the logical processors; a debug unit to perform debug operations and collect debug data related to execution of the program code; a performance monitoring unit (PMU) comprising a plurality of counter registers, the PMU to collect performance data related to execution of the program code; and a plurality of trigger units, each trigger unit associated with a logical processor of the plurality of logical processors and configured to communicate trigger event data to the processor trace circuitry in response to trigger events received from at least one of the debug unit and the PMU in accordance with values of configuration bits in a corresponding trigger unit configuration register.

公开(公告)号：US20200210320A1

公开(公告)日：2020-07-02

申请号：US16235489

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Beeman STRONG ,  Matthew C. MERTEN ,  Jason AGRON

IPC: G06F11/36

Abstract: A method for tracing software code executing on a core of a processor is described. The method includes generating a set of packets for a trace packet stream based on a main cycle counter, which maintains a count of cycles elapsing in the core since a packet was emitted into the trace packet stream, and a commit cycle counter, which maintains a cycle count in the core since the last commit operation, wherein the generating comprises (1) storing a value of the main cycle counter in the commit cycle counter in response to detecting a commit operation and (2) storing a value of the commit cycle counter in the main cycle counter in response to detecting an abort in the core; and emitting the set of packets from the processor into the trace packet stream for tracing execution of the software code.