公开(公告)号：US11734457B2

公开(公告)日：2023-08-22

申请号：US16724555

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Neel Piyush Shah ,  Enrico David Carrieri ,  Aditya Katragada ,  Jonathan Mark Lutz ,  Michael Carl Neve de Mevergnies ,  Bhavana Prabhakar

IPC: G06F21/71 ,  G06F11/36 ,  G06F21/31 ,  G06F21/79

CPC classification number: G06F21/71 ,  G06F11/3656 ,  G06F21/31 ,  G06F21/79

Abstract: A processor that was manufactured by a manufacturer comprises privileged debug operational circuitry, a debug restriction fuse, a credential store, a credential of the manufacturer in the credential store, and debug control circuitry. The debug restriction fuse is a one-time programmable fuse. The debug control circuitry is to automatically restrict access to the privileged debug operational circuitry, based on the debug restriction fuse. The processor may also include public debug operational circuitry, a prevent-unauthorized-debug (PUD) fuse, and an undo-PUD fuse. When the PUD fuse is set and the undo-PUD fuse is clear, the debug control circuitry may respond to an attempt by a debugger to use the public debug operational circuitry by determining whether the debugger is authorized, disallowing access if the debugger is not authorized, and allowing access if the debugger is authorized. Other embodiments are described and claimed.

公开(公告)号：US20240056448A1

公开(公告)日：2024-02-15

申请号：US18478661

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Anand Venkitasubramani ,  Michael Carl Neve de Mevergnies

IPC: H04L9/40

CPC classification number: H04L63/10

Abstract: Systems or methods of the present disclosure may provide a system that includes a secure processor subsystem that includes a processor and a first programmable lookup table. The first programmable lookup table is to receive global identifiers for initiators of operations using a resource and to translate the global identifiers to respective local identifiers for use in the secure processor subsystem. The initiators are external to the secure processor subsystem. The secure processor subsystem also includes a second programmable lookup table to translate the local identifiers to respective global identifiers for egresses from the secure processor subsystem.