公开(公告)号：US09973417B2

公开(公告)日：2018-05-15

申请号：US15256390

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： Keith D. Underwood ,  Steffen Kosinski ,  Jaroslaw Topp ,  Jan Norden ,  Michael Redeker

IPC: H04L29/04 ,  H04L12/721 ,  G06F15/167 ,  G06F13/38 ,  H04L12/773 ,  H04L1/12 ,  H04L12/26 ,  H04L12/801 ,  H04L29/08 ,  H04L1/18

CPC classification number: H04L45/38 ,  G06F13/385 ,  G06F15/167 ,  H04L1/12 ,  H04L1/1835 ,  H04L43/103 ,  H04L45/60 ,  H04L47/34 ,  H04L67/10 ,  Y02D10/14 ,  Y02D10/151

Abstract: Methods related to communication between and within nodes in a high performance computing system are presented. Processing time for message exchange between a processing unit and a network controller interface in a node is reduced. Resources required to manage application state in the network interface controller are minimized. In the network interface controller, multiple contexts are multiplexed into one physical Direct Memory Access engine. Virtual to physical address translation in the network interface controller is accelerated by using a plurality of independent caches, with each level of the page table hierarchy cached in an independent cache. A memory management scheme for data structures distributed between the processing unit and the network controller interface is provided. The state required to implement end-to-end reliability is reduced by limiting the transmit sequence number space to the currently in-flight messages.