公开(公告)号：US10579535B2

公开(公告)日：2020-03-03

申请号：US15843292

申请日：2017-12-15

Applicant: Intel Corporation

Inventor： Lihu Rappoport ,  Jared Warner Stark, IV ,  Franck Sala ,  Michael Tal ,  Gil Shmueli ,  Adrian Flesler

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0855 ,  G06F1/3246 ,  G06F9/30 ,  G06F12/126

Abstract: A processor includes a processor core and a micro-op cache communicably coupled to the processor core. The micro-op cache includes a micro-op tag array, wherein tag array entries in the micro-op tag array are indexed according to set and way of set-associative cache, and a micro-op data array to store multiple micro-ops. The data array entries in the micro-op data array are indexed according to bank number of a plurality of cache banks and to a set within one cache bank of the plurality of cache banks.

公开(公告)号：US20190188142A1

公开(公告)日：2019-06-20

申请号：US15843292

申请日：2017-12-15

Applicant: Intel Corporation

Inventor： Lihu RAPPOPORT ,  Jared Warner Stark iv ,  Franck Sala ,  Michael Tal ,  Gil Shmueli ,  Adrian Flesler

IPC: G06F12/0891 ,  G06F12/0855 ,  G06F1/32 ,  G06F9/30

Abstract: A processor includes a processor core and a micro-op cache communicably coupled to the processor core. The micro-op cache includes a micro-op tag array, wherein tag array entries in the micro-op tag array are indexed according to set and way of set-associative cache, and a micro-op data array to store multiple micro-ops. The data array entries in the micro-op data array are indexed according to bank number of a plurality of cache banks and to a set within one cache bank of the plurality of cache banks.