公开(公告)号：US20190188142A1

公开(公告)日：2019-06-20

申请号：US15843292

申请日：2017-12-15

Applicant: Intel Corporation

Inventor： Lihu RAPPOPORT ,  Jared Warner Stark iv ,  Franck Sala ,  Michael Tal ,  Gil Shmueli ,  Adrian Flesler

IPC: G06F12/0891 ,  G06F12/0855 ,  G06F1/32 ,  G06F9/30

Abstract: A processor includes a processor core and a micro-op cache communicably coupled to the processor core. The micro-op cache includes a micro-op tag array, wherein tag array entries in the micro-op tag array are indexed according to set and way of set-associative cache, and a micro-op data array to store multiple micro-ops. The data array entries in the micro-op data array are indexed according to bank number of a plurality of cache banks and to a set within one cache bank of the plurality of cache banks.

公开(公告)号：US20210019149A1

公开(公告)日：2021-01-21

申请号：US16729349

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： ADARSH CHAUHAN ,  Franck SALA ,  Jayesh GAUR ,  Zeev SPERBER ,  Lihu RAPPOPORT ,  Adi YOAZ ,  Sreenivas SUBRAMONEY

IPC: G06F9/38 ,  G06F9/30

Abstract: Systems, methods, and apparatuses relating to hardware for auto-predication of critical branches. In one embodiment, a processor core includes a decoder to decode instructions into decoded instructions, an execution unit to execute the decoded instructions, a branch predictor circuit to predict a future outcome of a branch instruction, and a branch predication manager circuit to disable use of the predicted future outcome for a conditional critical branch comprising the branch instruction.

公开(公告)号：US20210200550A1

公开(公告)日：2021-07-01

申请号：US16729367

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Alexey Yurievich SIVTSOV ,  Franck SALA ,  Jared Warner STARK, IV ,  Lihu RAPPOPORT

IPC: G06F9/38 ,  G06F9/30

Abstract: Disclosed embodiments relate to systems and methods structured to predict a loop exit. In one example, a processor includes a branch prediction unit to determine a loop exit predictor start corresponding to a finite consistent loop, and an instruction decoder queue to: receive an iteration of the finite consistent loop corresponding to a loop exit predictor and an iteration count, replay one or more instructions of the iteration based on the iteration count, and switch to post-loop instructions responsive to a determination that a number of iterations of the finite consistent loop is equal to the iteration count.

公开(公告)号：US20230315453A1

公开(公告)日：2023-10-05

申请号：US17712018

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Ahmad YASIN ,  Lihu RAPPOPORT ,  Nir TELL ,  Rami BUSOOL ,  Eyal HADAS ,  Michael CHYNOWETH ,  Joseph OLIVAS ,  Christopher M. CHRULSKI

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/3867

Abstract: An instruction pipeline includes a circuit that can generate a hardware event to indicate conditional branches, including the direction of taken branches. The circuit can generate a forward conditional branch indicator for an opcode when a conditional branch is taken to a forward location from the opcode. The instruction pipeline includes a counter to increment in response to the forward conditional branch indicator, which will indicate a frequency of forward conditional branches for the opcode.

公开(公告)号：US20210200538A1

公开(公告)日：2021-07-01

申请号：US16729362

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Franck SALA ,  Lihu RAPPOPORT

IPC: G06F9/22 ,  G06F9/38 ,  G06F12/0871

Abstract: Disclosed embodiments relate to systems and methods to dually write micro-ops to a micro-op queue. A processor includes a micro-op cache communicatively coupled, via a first write port, to a micro-op queue, and a legacy fetch and decode pipeline communicatively coupled, via a second write port, to the micro-op queue, the processor to determine whether the micro-op cache stores a thread, the thread comprising a micro-op to be written to the micro-op queue, determine whether the legacy fetch and decode pipeline stores the thread if the micro-op cache does not store the thread, and write, via the micro-op queue, the micro-op from the thread to the micro-op queue responsive to the determination of whether the micro-op cache or the legacy fetch and decode pipeline stores the thread.