公开(公告)号：US20180047808A1

公开(公告)日：2018-02-15

申请号：US15789315

申请日：2017-10-20

Applicant: Intel Corporation

Inventor： Milton Clair WEBB ,  Mark BOHR ,  Tahir GHANI ,  Szuya S. LIAO

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L27/092 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L29/0649 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

公开(公告)号：US20190326391A1

公开(公告)日：2019-10-24

申请号：US16398995

申请日：2019-04-30

Applicant: Intel Corporation

Inventor： Milton Clair WEBB ,  Mark BOHR ,  Tahir GHANI ,  Szuya S. LIAO

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L29/78 ,  H01L23/535 ,  H01L29/417

Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.