公开(公告)号：US20200004538A1

公开(公告)日：2020-01-02

申请号：US16024849

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： Kermin E. FLEMING, JR. ,  Ping ZOU ,  Mitchell DIAMOND ,  Benjamin KEEN

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/82 ,  G06F9/50

Abstract: Systems, methods, and apparatuses relating to conditional operations in a configurable spatial accelerator are described. In one embodiment, a hardware accelerator includes an output buffer of a first processing element coupled to an input buffer of a second processing element via a first data path that is to send a first dataflow token from the output buffer of the first processing element to the input buffer of the second processing element when the first dataflow token is received in the output buffer of the first processing element; an output buffer of a third processing element coupled to the input buffer of the second processing element via a second data path that is to send a second dataflow token from the output buffer of the third processing element to the input buffer of the second processing element when the second dataflow token is received in the output buffer of the third processing element; a first backpressure path from the input buffer of the second processing element to the first processing element to indicate to the first processing element when storage is not available in the input buffer of the second processing element; a second backpres sure path from the input buffer of the second processing element to the third processing element to indicate to the third processing element when storage is not available in the input buffer of the second processing element; and a scheduler of the second processing element to cause storage of the first dataflow token from the first data path into the input buffer of the second processing element when both the first backpres sure path indicates storage is available in the input buffer of the second processing element and a conditional token received in a conditional queue of the second processing element from another processing element is a first value.

公开(公告)号：US20200233814A1

公开(公告)日：2020-07-23

申请号：US16786815

申请日：2020-02-10

Applicant: Intel Corporation

Inventor： Farah E. FARGO ,  Mitchell DIAMOND ,  David KEPPEL ,  Samantika S. SURY ,  Binh PHAM ,  Shobha VISSAPRAGADA

IPC: G06F12/1027

Abstract: Examples described herein relate to a computing system supporting custom page sized ranges for an application to map contiguous memory regions instead of many smaller sized pages. An application can request a custom range size. An operating system can allocate a contiguous physical memory region to a virtual address range by specifying a custom range sizes that are larger or smaller than the normal general page sizes. Virtual-to-physical address translation can occur using an address range circuitry and translation lookaside buffer in parallel. The address range circuitry can determine if a custom entry is available to use to identify a physical address translation for the virtual address. Physical address translation can be performed by transforming the virtual address in some examples.

公开(公告)号：US20220107911A1

公开(公告)日：2022-04-07

申请号：US17550875

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Kermin E. FLEMING ,  Simon C. STEELY ,  Kent D. GLOSSOP ,  Mitchell DIAMOND ,  Benjamin KEEN ,  Dennis BRADFORD ,  Fabrizio Petrini ,  Barry TANNENBAUM ,  Yongzhi ZHANG

IPC: G06F13/40 ,  G06F9/30 ,  G06F15/78

Abstract: Systems, methods, and apparatuses relating to operations in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value.

公开(公告)号：US20200004690A1

公开(公告)日：2020-01-02

申请号：US16024802

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： Suresh MATHEW ,  Mitchell DIAMOND ,  Kermin E. FLEMING, JR.

IPC: G06F12/1027 ,  G06F3/06

Abstract: Systems, methods, and apparatuses relating to low latency communications in a configurable spatial accelerator are described. In one embodiment, a processor includes a spatial array of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, a plurality of request address file circuits coupled to the spatial array of processing elements and a cache memory, each request address file circuit of the plurality of request address file circuits to access data in the cache memory in response to a request for data access from the spatial array of processing elements, a plurality of translation lookaside buffers comprising a translation lookaside buffer in each of the plurality of request address file circuits to provide an output of a physical address for an input of a virtual address, and a function controller to receive an interrupt that includes a first field, that when set to a first value, causes a shootdown message to be broadcast to the plurality of translation lookaside buffers to cause a shootdown in the plurality of translation lookaside buffers