公开(公告)号：US20170168118A1

公开(公告)日：2017-06-15

申请号：US15357312

申请日：2016-11-21

Applicant: INTEL CORPORATION

Inventor： Efraim Rotem ,  NIR ROSENZWEIG ,  JEFFREY A. CARLSON ,  PHILIP R. LEHWALDER ,  NADAV SHULMAN ,  Doron Rajwan

IPC: G01R31/36 ,  G01R22/10 ,  G01R21/133

CPC classification number: G01R31/3648 ,  G01R21/133 ,  G01R22/10 ,  G01R31/3624

Abstract: Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal. Other examples are described and claimed.

公开(公告)号：US20160085263A1

公开(公告)日：2016-03-24

申请号：US14492179

申请日：2014-09-22

Applicant: Intel Corporation

Inventor： TAL KUZI ,  NADAV SHULMAN ,  OFER J. NATHAN ,  ORI LEVY ,  ITAI FEIT

IPC: G06F1/14 ,  G06F11/16

CPC classification number: G06F1/14 ,  G06F9/50 ,  G06F11/1658 ,  G06F2201/835

Abstract: In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括用于存储处理器的时间戳计数的主计数器，以及多个核心，每个核心包括用于存储核心时间戳计数的核心计数器。 处理器还包括响应于核心中的去同步事件的同步逻辑：获得主计数器的值; 使用主计数器的值来启动第一核心计数器，其中第一核心计数器包括在第一核心中; 将第一核心计数器的同步数字与指示主计数器的同步数字的值的同步信号进行比较; 并且响应于所述同步数字与所述同步信号不匹配的确定，基于所述同步信号的等待时间值来调整所述第一核心计数器的第一数字子集。 描述和要求保护其他实施例。

公开(公告)号：US20210018971A1

公开(公告)日：2021-01-21

申请号：US17042804

申请日：2018-05-01

Applicant: Intel Corporation

Inventor： EFRAIM ROTEM ,  ELIEZER WEISSMANN ,  ERIC DEHAEMER ,  ALEXANDER GENDLER ,  NADAV SHULMAN ,  KRISHNAKANTH SISTLA ,  NIR ROSENZWEIG ,  ANKUSH VARMA ,  ARIEL SZAPIRO ,  ARYE ALBAHARI ,  IDO MELAMED ,  NIR MISGAV ,  VIVEK GARG ,  NIMROD ANGEL ,  ADWAIT PURANDARE ,  ELKANA KOREM

IPC: G06F1/329 ,  G06F1/3206 ,  G06F9/48 ,  G06F9/30 ,  G06F9/4401

Abstract: A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.