公开(公告)号：US20200293456A1

公开(公告)日：2020-09-17

申请号：US16354859

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： MURALI RAMADOSS ,  VIKRANTH VEMULAPALLI ,  NIRAN COORAY ,  WILLIAM B. SADLER ,  JONATHAN D. PEARCE ,  MARIAN ALIN PETRE ,  BEN ASHBAUGH ,  ELMOUSTAPHA OULD-AHMED-VALL ,  NICOLAS GALOPPO VON BORRIES ,  ALTUG KOKER ,  ARAVINDH ANANTARAMAN ,  SUBRAMANIAM MAIYURAN ,  VARGHESE GEORGE ,  SUNGYE KIM ,  ANDREI VALENTIN

IPC: G06F12/1009 ,  G06N20/00

Abstract: Methods and apparatus relating to predictive page fault handling. In an example, an apparatus comprises a processor to receive a virtual address that triggered a page fault for a compute process, check a virtual memory space for a virtual memory allocation for the compute process that triggered the page fault and manage the page fault according to one of a first protocol in response to a determination that the virtual address that triggered the page fault is a last page in the virtual memory allocation for the compute process, or a second protocol in response to a determination that the virtual address that triggered the page fault is not a last page in the virtual memory allocation for the compute process. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200293365A1

公开(公告)日：2020-09-17

申请号：US16354919

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： NIRAN COORAY ,  WILLIAM B. SADLER ,  JONATHAN D. PEARCE ,  MARIAN ALIN PETRE ,  BEN ASHBAUGH ,  MURALI RAMADOSS ,  VIKRANTH VEMULAPALLI ,  ANKUR N SHAH ,  RAJESH SANKARAN

IPC: G06F9/48 ,  G06T1/60 ,  G06T1/20 ,  G06F12/1009

Abstract: Methods and apparatus relating to transactional page fault handling. In an example, an apparatus comprises a processor to divide an execution thread of a graphics workload into a set of transactions which are to be executed atomically, initiate the execution of the thread, and manage the execution of the thread according to one of a first protocol in response to a determination that a page fault occurred in the execution of a transaction, or a second protocol in response to a determination that a page fault did not occur in the execution of a transaction. Other embodiments are also disclosed and claimed.