公开(公告)号：US20200265545A1

公开(公告)日：2020-08-20

申请号：US16853405

申请日：2020-04-20

Applicant: Intel Corporation

Inventor： Naveen MELLEMPUDI ,  DHEEVATSA MUDIGERE ,  DIPANKAR DAS ,  SRINIVAS SRIDHARAN

IPC: G06T1/20 ,  G06N3/08 ,  G06N3/04 ,  G06F7/544 ,  G06F17/15 ,  G06F7/501 ,  G06F5/01 ,  G06F7/523 ,  G06F17/16 ,  G06N3/063

Abstract: One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising compute unit including a hardware logic unit having dynamic precision fixed-point logic, the compute unit to receive a set of dynamic fixed-point tensors, compute, via the dynamic precision fixed-point logic, a right-shift value using an absolute maximum value within the set of dynamic fixed-point tensors and a dynamic range of the set of dynamic fixed-point tensors, right-shift data values within the set of dynamic fixed-point tensors based on the right-shift value, increment a shared exponent associated with the set of dynamic fixed-point tensors based on the right-shift value, perform a compute operation on the set of dynamic fixed-point tensors, and generate an output tensor via the compute operation on the set of dynamic fixed-point tensors.

公开(公告)号：US20210072955A1

公开(公告)日：2021-03-11

申请号：US16562979

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Naveen MELLEMPUDI ,  Dipankar DAS ,  Chunhui MEI ,  Kristopher WONG ,  Dhiraj D. KALAMKAR ,  Hong H. JIANG ,  Subramaniam Maiyuran ,  Varghese George

IPC: G06F7/499 ,  G06F17/16 ,  G06N3/08 ,  G06N3/04 ,  G06T1/20

Abstract: An apparatus to facilitate a computer number format conversion is disclosed. The apparatus comprises a control unit to receive to receive data format information indicating a first precision data format that input data is to be received and converter hardware to receive the input data and convert the first precision data format to a second precision data format based on the data format information.

公开(公告)号：US20240241722A1

公开(公告)日：2024-07-18

申请号：US18619570

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Naveen MELLEMPUDI ,  Alexander F. HEINECKE ,  Robert VALENTINE ,  Mark J. CHARNEY ,  Christopher J. HUGHES ,  Evangelos GEORGANAS ,  Zeev SPERBER ,  Amit GRADSTEIN ,  Simon RUBANOVICH

IPC: G06F9/30 ,  G06F7/499 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F7/49915 ,  G06F9/30196 ,  G06F9/3887

Abstract: Systems, methods, and apparatuses relating to 8-bit floating-point matrix dot product instructions are described. A processor embodiment includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a destination matrix having single-precision elements, a first source matrix, and a second source matrix, the source matrices having elements that each comprise a quadruple of 8-bit floating-point values, the opcode to indicate execution circuitry is to cause, for each element of the first source matrix and corresponding element of the second source matrix, a conversion of the 8-bit floating-point values to single-precision values, a multiplication of different pairs of converted single-precision values to generate plurality of results, and an accumulation of the results with previous contents of a corresponding element of the destination matrix, decode circuitry to decode the fetched instruction, and the execution circuitry to respond to the decoded instruction as specified by the opcode.

公开(公告)号：US20210110508A1

公开(公告)日：2021-04-15

申请号：US17083588

申请日：2020-10-29

Applicant: Intel Corporation

Inventor： Naveen MELLEMPUDI ,  DHEEVATSA MUDIGERE ,  DIPANKAR DAS ,  SRINIVAS SRIDHARAN

IPC: G06T1/20 ,  G06N3/063 ,  G06F17/16 ,  G06F7/523 ,  G06F5/01 ,  G06F7/501 ,  G06F17/15 ,  G06N3/04 ,  G06F7/544 ,  G06N3/08

Abstract: One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising compute unit including a hardware logic unit having dynamic precision fixed-point logic, the compute unit to receive a set of dynamic fixed-point tensors, compute, via the dynamic precision fixed-point logic, a right-shift value using an absolute maximum value within the set of dynamic fixed-point tensors and a dynamic range of the set of dynamic fixed-point tensors, right-shift data values within the set of dynamic fixed-point tensors based on the right-shift value, increment a shared exponent associated with the set of dynamic fixed-point tensors based on the right-shift value, perform a compute operation on the set of dynamic fixed-point tensors, and generate an output tensor via the compute operation on the set of dynamic fixed-point tensors.

公开(公告)号：US20180322607A1

公开(公告)日：2018-11-08

申请号：US15881991

申请日：2018-01-29

Applicant: Intel Corporation

Inventor： Naveen MELLEMPUDI ,  DHEEVATSA MUDIGERE ,  DIPANKAR DAS ,  SRINIVAS SRIDHARAN

IPC: G06T1/20 ,  G06N3/063 ,  G06F17/16 ,  G06F17/15 ,  G06F5/01 ,  G06F7/501 ,  G06F7/523

CPC classification number: G06T1/20 ,  G06F5/01 ,  G06F7/501 ,  G06F7/523 ,  G06F17/153 ,  G06F17/16 ,  G06N3/063

Abstract: One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising compute unit including a hardware logic unit having dynamic precision fixed-point logic; a decode unit to decode an instruction for execution by the compute unit, the instruction to cause the compute unit to perform a matrix arithmetic operation on a set of dynamic fixed-point tensors; and a dynamic precision manager to dynamically adjust the precision of a compute operation performed by the compute unit during the matrix arithmetic operation, the dynamic precision manager to adjust the precision of the compute operation to prevent an arithmetic overflow.