公开(公告)号：US20230103206A1

公开(公告)日：2023-03-30

申请号：US17448806

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Niranjan Soundararajan ,  Sreenivas Subramoney ,  Neelu Shivprakash Kalani ,  Vishal Gupta

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

Abstract: In an embodiment, a processor may include an execution circuit to execute a plurality of instructions, a cache, and a decode circuit. The decode circuit may be to: detect a branch instruction in a program, the branch instruction to cause execution to follow either a first path or a second path in the program; and in response to a determination that the branch instruction is a hard to predict (HTP) branch, cause first and second sets of instructions to be stored in the cache, where the first set of instructions is included in the first path, and where the second set of instructions is included in the second path. Other embodiments are described and claimed.

公开(公告)号：US20230418757A1

公开(公告)日：2023-12-28

申请号：US17846688

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Niranjan Soundararajan ,  Sreenivas Subramoney ,  Vishal Gupta ,  Neelu Shivprakash Kalani

IPC: G06F12/0891 ,  G06F12/0831 ,  G06F12/0871 ,  G06F9/30

CPC classification number: G06F12/0891 ,  G06F12/0833 ,  G06F12/0871 ,  G06F9/30145 ,  G06F9/30047

Abstract: Techniques and mechanisms for selectively increasing or decreasing an amount of cache resources which are to be available for use in the provisioning of decoded micro-operations in a processor. In an embodiment, a processor core comprises both a first cache which is dedicated to caching micro-operations, and a second cache which is coupled to receive data, or non-decoded instructions. The core further comprises circuitry to monitor one or more cache performance characteristics of the core. Based on the one or more cache performance characteristics, the circuitry performs an evaluation to determine whether to increase—or alternatively, to decrease—the size of a pool of one or more caches which are to be available to receive micro-operations. In another embodiment, the second cache is added to the pool based on an indication of an overutilization of the first cache.