公开(公告)号：US20240098514A1

公开(公告)日：2024-03-21

申请号：US18514418

申请日：2023-11-20

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Valerie J. Parker ,  Vishal Gupta ,  Patrick L. Connor ,  Kevin W. Bross

IPC: H04W16/18 ,  H04L5/00 ,  H04W40/22

CPC classification number: H04W16/18 ,  H04L5/0048 ,  H04W40/22

Abstract: Various approaches for the deployment and coordination of network operation processing, compute processing, and communications for 5G networks, including with the use of fingerprint-based vRAN cell integrity monitoring, are discussed. In an example, analyzing a state of a 5G network includes: obtaining initial fingerprint reference data of a network state between a virtualized radio access network (vRAN) node and at least one fingerprint reference unit (FRU) device wirelessly connected to the vRAN node; comparing the initial fingerprint reference data to subsequent fingerprint data of the network state between the vRAN node (e.g., operating as vRAN gNB, or as an IAB Donor or IAB Node) and the at least one FRU device to detect a changed network condition; and performing an action at the vRAN node to modify or disable a component of the 5G network, in response to detection of the changed network condition.

公开(公告)号：US20230103206A1

公开(公告)日：2023-03-30

申请号：US17448806

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Niranjan Soundararajan ,  Sreenivas Subramoney ,  Neelu Shivprakash Kalani ,  Vishal Gupta

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

Abstract: In an embodiment, a processor may include an execution circuit to execute a plurality of instructions, a cache, and a decode circuit. The decode circuit may be to: detect a branch instruction in a program, the branch instruction to cause execution to follow either a first path or a second path in the program; and in response to a determination that the branch instruction is a hard to predict (HTP) branch, cause first and second sets of instructions to be stored in the cache, where the first set of instructions is included in the first path, and where the second set of instructions is included in the second path. Other embodiments are described and claimed.

公开(公告)号：US20250081004A1

公开(公告)日：2025-03-06

申请号：US18583609

申请日：2024-02-21

Applicant: Intel Corporation

Inventor： Valerie J. Parker ,  Stephen T. Palermo ,  Vishal Gupta ,  Patrick L. Connor

IPC: H04W24/04 ,  H04W24/10 ,  H04W84/04

Abstract: Various approaches for the deployment and coordination of network operation processing, communications, and mobile device positioning, in connection with backhaul of a radio access network (RAN), are disclosed. An example method of operation of backhaul communications used with a radio access network (RAN) includes: obtaining measurements corresponding to wireless communications of a radio access network (RAN) operating with a backhaul, the measurements based on in-phase and quadrature (IQ) data of the wireless communications; performing a comparison of the measurements to an expected operational state of the RAN, with the expected operational state being established from a baseline of the IQ data collected in the RAN; and modifying the wireless communications of the backhaul based on the comparison of the measurements to the expected operational state.

公开(公告)号：US20230418757A1

公开(公告)日：2023-12-28

申请号：US17846688

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Niranjan Soundararajan ,  Sreenivas Subramoney ,  Vishal Gupta ,  Neelu Shivprakash Kalani

IPC: G06F12/0891 ,  G06F12/0831 ,  G06F12/0871 ,  G06F9/30

CPC classification number: G06F12/0891 ,  G06F12/0833 ,  G06F12/0871 ,  G06F9/30145 ,  G06F9/30047

Abstract: Techniques and mechanisms for selectively increasing or decreasing an amount of cache resources which are to be available for use in the provisioning of decoded micro-operations in a processor. In an embodiment, a processor core comprises both a first cache which is dedicated to caching micro-operations, and a second cache which is coupled to receive data, or non-decoded instructions. The core further comprises circuitry to monitor one or more cache performance characteristics of the core. Based on the one or more cache performance characteristics, the circuitry performs an evaluation to determine whether to increase—or alternatively, to decrease—the size of a pool of one or more caches which are to be available to receive micro-operations. In another embodiment, the second cache is added to the pool based on an indication of an overutilization of the first cache.