公开(公告)号：US20220188000A1

公开(公告)日：2022-06-16

申请号：US17688611

申请日：2022-03-07

Applicant: Intel Corporation

Inventor： Nishant Singh ,  Sharada Venkateswaran ,  Daniel Liu

IPC: G06F3/06

Abstract: An embodiment of an apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including a read data buffer, a content-addressable memory, and circuitry to track both prefetch read requests and non-prefetch read requests for a memory with the content-addressable memory and to store both prefetch entries and non-prefetch entries in the read data buffer. Other embodiments are disclosed and claimed.

公开(公告)号：US20220011939A1

公开(公告)日：2022-01-13

申请号：US17484296

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Nishant Singh ,  Daniel W. Liu ,  Sharada Venkateswaran

IPC: G06F3/06 ,  G06F11/07

Abstract: Technologies for memory mirroring across an interconnect are disclosed. In the illustrative embodiment, a primary memory agent that controls a single memory channel can implement memory mirroring by sending mirrored memory operations to a secondary memory agent over an interconnect. In the illustrative embodiment, the secondary memory agent may not be aware that it is performing mirrored memory operations. The primary memory agent may handle error recovery, scrubbing, and failover to the secondary memory agent.

公开(公告)号：US20240004808A1

公开(公告)日：2024-01-04

申请号：US17855213

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Sai Prashanth Muralidhara ,  Narasimha Sridhar Srirangam ,  Rawan Abdel Khalek ,  Yedidya Hilewitz ,  Daniel Liu ,  Sharada Venkateswaran ,  Wolf Witt ,  Nishant Singh

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  G06F2213/16

Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed prioritizing memory requests from core processors such that some memory transaction requests receive a higher priority than other memory transaction requests. In some embodiments, queue lengths and latency, frequency of core demand transaction prioritization and the like are monitored and prioritization throttled accordingly. Other embodiments may be described and/or claimed.

公开(公告)号：US11669454B2

公开(公告)日：2023-06-06

申请号：US16405691

申请日：2019-05-07

Applicant: Intel Corporation

Inventor： Vedaraman Geetha ,  Jeffrey Baxter ,  Sai Prashanth Muralidhara ,  Sharada Venkateswaran ,  Daniel Liu ,  Nishant Singh ,  Bahaa Fahim ,  Samuel D. Strom

IPC: G06F12/0817

CPC classification number: G06F12/0817 ,  G06F2212/1021 ,  G06F2212/608

Abstract: A processor includes one or more cores having cache, a cache home agent (CHA), a near memory controller, to near memory, and a far memory controller, which is to: receive a first memory read operation from the CHA directed at a memory address; detect a miss for the first memory address at the near memory; issue a second memory read operation to the far memory controller to retrieve a cache line, having first data, from the memory address of far memory; receive the cache line from the far memory controller in response to the second memory read operation; and send the cache line to the CHA with a forced change to a directory state of the cache line at the CHA, the forced change to cause the CHA to snoop remote sockets to maintain data coherence for the cache line in an absence of directory state in the far memory.