公开(公告)号：US10809669B2

公开(公告)日：2020-10-20

申请号：US16600794

申请日：2019-10-14

Applicant: Intel Corporation

Inventor： Gil Horovitz ,  Aryeh Farber ,  Nisim Machluf ,  Evgeny Shumaker ,  Igal Kushnir

IPC: G04F10/00 ,  H03L7/083 ,  H03L7/095 ,  H03L7/08

Abstract: Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by a delay. Gate circuitry generates a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired delay.

公开(公告)号：US10474110B1

公开(公告)日：2019-11-12

申请号：US16229638

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Gil Horovitz ,  Aryeh Farber ,  Nisim Machluf ,  Evgeny Shumaker ,  Igal Kushnir

IPC: G04F10/00 ,  H03L7/083 ,  H03L7/095 ,  H03L7/08

Abstract: Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by an incremental delay. Gate circuitry outputs a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the incremental delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired incremental delay.