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公开(公告)号：US11824576B2
公开(公告)日：2023-11-21
申请号：US17030832
申请日：2020-09-24
Applicant: Intel Corporation
Inventor： Ofir Degani , Gil Horovitz , Evgeny Shumaker , Sergey Bershansky , Aryeh Farber , Igor Gertman , Run Levinger
Abstract: An apparatus for generating an output oscillator signal is provided. The apparatus includes a deviation determining circuitry configured to generate a deviation signal based on a first comparison signal and a second comparison signal. Further, the apparatus includes a first oscillator configured to generate the output oscillator signal based on the deviation signal and a second oscillator signal from a second, resonator-based oscillator. The first comparison signal is based on the second oscillator signal or the output oscillator signal. The second oscillator signal has a frequency of at least 1 GHz. The second comparison signal is based on a third oscillator signal from a third oscillator. The third oscillator signal has a frequency lower than 1 GHz.
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公开(公告)号：US20210050857A1
公开(公告)日：2021-02-18
申请号：US17066490
申请日：2020-10-09
Applicant: Intel Corporation
Inventor： Gil Horovitz , Sharon Malevsky , Evgeny Shumaker , Igal Kushnir
Abstract: Systems, methods, and circuitries are provided to generate a radio frequency (RF) signal having a desired radio frequency fRF. In one example a frequency synthesizer system includes a clock, an opportunistic phase locked loop (PLL), and an RF PLL. The clock circuitry is configured to generate a clock signal having a frequency fXTL. The opportunistic phase locked loop (PLL) is configured to generate a reference signal having a reference frequency fREF that is close to a free-running frequency of an oscillator in the opportunistic PLL. The opportunistic PLL is configured to synchronize the reference signal to the clock signal. The RF PLL is configured to generate the RF signal having the desired radio frequency and to synchronize the RF signal with the reference signal.
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公开(公告)号：US20200295765A1
公开(公告)日：2020-09-17
申请号：US16352043
申请日：2019-03-13
Applicant: Intel Corporation
Inventor： Abhishek Agrawal , Alon Cohen , Gil Horovitz , Somnath Kundu , Run Levinger , Stefano Pellerano , Jahnavi Sharma , Evgeny Shumaker , Izhak Hod
Abstract: A quadrature based voltage controlled oscillator (VCO) local oscillator (LO) system is disclosed. The system includes a phase detector, a quadrature phase VCO, a quadrature control path, an in-phase control path, and an in-phase VCO. The phase detector is configured to compare and generate phase error between a reference clock and an in-phase VCO output. The quadrature control path configured to generate a quadrature control voltage based on a quadrature VCO output and the in-phase VCO output. The quadrature phase VCO configured to generate the quadrature VCO output based on the quadrature control voltage and the generated phase error. The in-phase control path configured to generate an in-phase control voltage based on the quadrature VCO output and the in-phase VCO output. The in-phase VCO is configured to generate the in-phase VCO output based on the in-phase control voltage and the generated phase error. An all digital dual mode phase locked/phase tracking loop LO generate system is also disclosed.
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4.发明授权公开(公告)号：US10103761B2
公开(公告)日：2018-10-16
申请号：US15275779
申请日：2016-09-26
Applicant: Intel Corporation
Inventor： Igal Kushnir , Gil Horovitz , Sarit Zur
Abstract: Control circuitry for use in generating a local oscillator (LO) signal is provided. Synthesizer control circuitry is configured to control synthesizer circuity to generate an analog oscillator signal having a first frequency at which phase noise is minimized. DS control circuitry is configured to generate a control word or message to cause DS circuitry to generate a digital DS signal having a desired frequency when the DS circuitry is clocked by the oscillator signal having the first frequency. The desired frequency is proportional to the LO signal frequency. The digital DS signal generated by the DS circuitry is used to generate the LO signal. Thus the first frequency used to clock the DS circuitry is selected to optimize the oscillator rather than having some relationship to the LO frequency. In addition, a single synthesizer may be used in order to simultaneously generate many LO signals.
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公开(公告)号：US12191871B2
公开(公告)日：2025-01-07
申请号：US17355217
申请日：2021-06-23
Applicant: Intel Corporation
Inventor： Evgeny Shumaker , Elan Banin , Ofir Degani , Gil Horovitz
Abstract: A TDC circuit configured to receive a reference clock (REF) signal and a signal derived from a LO; generate a plurality of digital values indicative of a measured phase difference between the signal derived from the LO and the REF signal, wherein each of the plurality of digital values are determined from a unique set of a plurality of sets of TDC measurement component quantization levels; generate a combined series of quantization levels based on a combination of the plurality of sets of TDC measurement component quantization levels; and determine a combined digital value from the combined series of quantization levels and at least one of the plurality of digital values to generate an output of the TDC circuit. The combined series of quantization levels may be generated by summing simultaneously occurring levels of each of the plurality of sets of TDC measurement component quantization levels together.
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Patent Agency Ranking
公开(公告)号：US10804911B2
公开(公告)日：2020-10-13
申请号：US16292717
申请日：2019-03-05
Applicant: Intel Corporation
Inventor： Gil Horovitz , Sharon Malevsky , Evgeny Shumaker , Igal Kushnir
Abstract: Systems, methods, and circuitries are provided to generate a radio frequency (RF) signal having a desired radio frequency fRF. In one example a frequency synthesizer system includes a clock, an opportunistic phase locked loop (PLL), and an RF PLL. The clock circuitry is configured to generate a clock signal having a frequency fXTL. The opportunistic phase locked loop (PLL) is configured to generate a reference signal having a reference frequency fREF that is close to a free-running frequency of an oscillator in the opportunistic PLL. The opportunistic PLL is configured to synchronize the reference signal to the clock signal. The RF PLL is configured to generate the RF signal having the desired radio frequency and to synchronize the RF signal with the reference signal.
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公开(公告)号：US20200177190A1
公开(公告)日：2020-06-04
申请号：US16204109
申请日：2018-11-29
Applicant: Intel Corporation
Inventor： Evgeny Shumaker , Gil Horovitz
Abstract: A phase locked loop (PLL) system for mitigating non-linear phase errors stemming from time-variant integral non-linearity of the LO feedback phase quantizer (TDC) is disclosed. The system includes a phase modulation circuit which is configured to generate a plurality of phase shifts for a reference signal; select a phase shift of the plurality of phase shifts and introduce the selected phase shift into the reference signal, thereby modulating the phase difference between the feedback and the reference signal. Alternatively, the above phase modulation can be applied on the feedback signal path, attaining equivalent results. TDC is configured to quantize the phase of the LO feedback signal relative to the shifted reference signal to generate a phase detection signal, effectively modulating the non-linearity contributed error away from the LO center frequency. The phase detection signal is then digitally compensated for the intentional fractional frequency shift to allow the PLL to generate LO signal the desired frequency.
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公开(公告)号：US10474110B1
公开(公告)日：2019-11-12
申请号：US16229638
申请日：2018-12-21
Applicant: Intel Corporation
Inventor： Gil Horovitz , Aryeh Farber , Nisim Machluf , Evgeny Shumaker , Igal Kushnir
Abstract: Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by an incremental delay. Gate circuitry outputs a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the incremental delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired incremental delay.
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公开(公告)号：US11558059B2
公开(公告)日：2023-01-17
申请号：US17004037
申请日：2020-08-27
Applicant: Intel Corporation
Inventor： Igal Kushnir , Evgeny Shumaker , Aryeh Farber , Gil Horovitz
Abstract: Examples relate to a digitally controlled oscillator circuit arrangement, a digitally controlled oscillation means, a method for a digitally controlled oscillator, a digital loop filter circuit arrangement, a digital loop filtering means, a method for a digital loop filter, a phase locked loop circuit arrangement and phase locked loop, a user device and a base station. The digitally controlled oscillator circuit arrangement comprises input circuitry for obtaining a frequency setting signal, the frequency setting signal comprising a plurality of signal components, selection circuitry for selecting one signal component of the plurality of signal components of the frequency setting signal based on an oscillation signal of the digitally controlled oscillator circuit arrangement, wherein the selection circuitry comprises counting circuitry and multiplexing circuitry, signal generation circuitry for generating the oscillation signal based on the selected signal component of the frequency setting signal, and output circuitry for providing the oscillation signal.
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公开(公告)号：US10809669B2
公开(公告)日：2020-10-20
申请号：US16600794
申请日：2019-10-14
Applicant: Intel Corporation
Inventor： Gil Horovitz , Aryeh Farber , Nisim Machluf , Evgeny Shumaker , Igal Kushnir
Abstract: Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by a delay. Gate circuitry generates a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired delay.
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