公开(公告)号：US20220100520A1

公开(公告)日：2022-03-31

申请号：US17033771

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Gilles Pokam ,  Jared Stark ,  Niranjan Kumar Soundararajan ,  Oleg Ladin

IPC: G06F9/38 ,  G06F12/0875

Abstract: Methods and apparatus relating to branch prefetch mechanisms for mitigating frontend branch resteers are described. In an embodiment, predecodes an entry in a cache to generate a predecoded branch operation. The entry is associated with a cold branch operation, where the cold branch operation corresponds to an operation that is detected for a first time after storage in an instruction cache and wherein the cold branch operation remains undecoded since it is stored at a location in a cache line prior to a subsequent location of a branch operation in the cache line. The predecoded branch operation is stored in a Branch Prefetch Buffer (BPB) in response to a cache line fill operation of the cold branch operation in an instruction cache. Other embodiments are also disclosed and claimed.

公开(公告)号：US11928472B2

公开(公告)日：2024-03-12

申请号：US17033771

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Gilles Pokam ,  Jared Warner Stark, IV ,  Niranjan Kumar Soundararajan ,  Oleg Ladin

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

CPC classification number: G06F9/3806 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/382 ,  G06F9/383 ,  G06F9/3844 ,  G06F12/0875 ,  G06F9/30145 ,  G06F2212/452

Abstract: Methods and apparatus relating to branch prefetch mechanisms for mitigating front-end branch resteers are described. In an embodiment, predecodes an entry in a cache to generate a predecoded branch operation. The entry is associated with a cold branch operation, where the cold branch operation corresponds to an operation that is detected for a first time after storage in an instruction cache and wherein the cold branch operation remains undecoded since it is stored at a location in a cache line prior to a subsequent location of a branch operation in the cache line. The predecoded branch operation is stored in a Branch Prefetch Buffer (BPB) in response to a cache line fill operation of the cold branch operation in an instruction cache. Other embodiments are also disclosed and claimed.