公开(公告)号：US12029021B2

公开(公告)日：2024-07-02

申请号：US17701419

申请日：2022-03-22

Applicant: Intel Corporation

Inventor： Peng Zheng ,  Varun Mishra ,  Tahir Ghani

IPC: H10B10/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66

CPC classification number: H10B10/12 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66545

Abstract: Embodiments disclosed herein include transistor devices with depopulated channels. In an embodiment, the transistor device comprises a source region, a drain region, and a vertical stack of semiconductor channels between the source region and the drain region. In an embodiment, the vertical stack of semiconductor channels comprises first semiconductor channels, and a second semiconductor channel over the first semiconductor channels. In an embodiment, first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel.

公开(公告)号：US11315934B2

公开(公告)日：2022-04-26

申请号：US16827570

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Peng Zheng ,  Varun Mishra ,  Tahir Ghani

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/36 ,  H01L29/167 ,  H01L21/306 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/265

Abstract: Embodiments disclosed herein include transistor devices with depopulated channels. In an embodiment, the transistor device comprises a source region, a drain region, and a vertical stack of semiconductor channels between the source region and the drain region. In an embodiment, the vertical stack of semiconductor channels comprises first semiconductor channels, and a second semiconductor channel over the first semiconductor channels. In an embodiment, first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel.

公开(公告)号：US20210398977A1

公开(公告)日：2021-12-23

申请号：US16905743

申请日：2020-06-18

Applicant: Intel Corporation

Inventor： Varun Mishra ,  Peng Zheng ,  Aaron Lilak ,  Tahir Ghani ,  Harold Kennel ,  Mauro Kobrinsky

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L27/11 ,  H01L21/8238

Abstract: Integrated circuitry comprising interconnect metallization on both front and back sides of a gate-all-around (GAA) transistor structure lacking at least one active bottom channel region. Bottom channel regions may be depopulated from a GAA transistor structure following removal of a back side substrate that exposes an inactive portion of a semiconductor fin. During back-side processing, one or more bottom channel region may be removed or rendered inactive through dopant implantation. Back-side processing may then proceed with the interconnection of one or more terminal of the GAA transistor structures through one or more levels of back-side interconnect metallization.