公开(公告)号：US20240321738A1

公开(公告)日：2024-09-26

申请号：US18125455

申请日：2023-03-23

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Prabhjot Kaur Luthra ,  Nidhi Khandelwal ,  Marie T. Conte ,  Saurabh Acharya ,  Shengsi Liu ,  Gary Allen ,  Clifford J. Engel ,  Charles H. Wallace

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L23/5283 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/778

Abstract: Techniques to form an integrated circuit having a bridging contact structure. A bridging contact structure may, for example, bridge between source/drain contacts and to an adjacent gate electrode within the same device layer. In an example, a gate cut structure extends in a first direction to separate the source or drain regions and gate structures of neighboring semiconductor devices. Contacts may be formed over the source or drain regions of the neighboring devices on opposite sides of the gate cut along a second direction orthogonal to the first direction. A portion of the gate cut is replaced with a first conductive bridge between the source or drain contacts. A portion of one or more dielectric barriers between one of the source or drain contacts and an adjacent gate electrode is replaced with a second conductive bridge in the first direction between the source or drain contact and the gate structure.

公开(公告)号：US20250113563A1

公开(公告)日：2025-04-03

申请号：US18478545

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Leonard Guler ,  Saurabh Acharya ,  Nidhi Khandelwal ,  Prabhjot Kaur Luthra ,  Sean Pursel ,  Izabela Anna Samek

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: In one embodiment, an integrated circuit structure includes a first transistor device comprising a first gate stack and a second transistor device comprising a second gate stack. The second transistor device is spaced a first distance laterally from the first transistor device. The structure further includes a dielectric region between the first gate stack and the second gate stack. The dielectric region is spaced a second distance laterally from the first transistor device, where the first distance is substantially twice the second distance.

公开(公告)号：US20240321872A1

公开(公告)日：2024-09-26

申请号：US18125447

申请日：2023-03-23

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Shengsi Liu ,  Saurabh Acharya ,  Thomas Obrien ,  Krishna Ganesan ,  Ankit Kirit Lakhani ,  Prabhjot Kaur Luthra ,  Nidhi Khandelwal ,  Clifford J. Engel ,  Baofu Zhu ,  Meenakshisundaram Ramanathan

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

Abstract: Techniques to form an integrated circuit having a gate cut between adjacent pairs of semiconductor devices. At least one of those adjacent pairs of semiconductor devices includes a conductive link (e.g., a bridge) through the gate cut to connect the adjacent gates together. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate of one semiconductor device from the gate of the other semiconductor device. A conductive link extends over a given gate cut to electrically connect the adjacent gate electrodes together. A dielectric layer extends over the bridged gate electrodes and the conductive link, and may have different thicknesses over those respective features.