公开(公告)号：US20230195464A1

公开(公告)日：2023-06-22

申请号：US17553780

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Anant Vithal Nori ,  Prathmesh Kallurkar ,  Sreenivas Subramoney ,  Niranjan Kumar Soundararajan

IPC: G06F9/38

CPC classification number: G06F9/3802

Abstract: Methods and apparatus relating to throttling a code fetch for speculative code paths are described. In an embodiment, a first storage structure stores a reference to a code line in response to a request to be received from a cache. A second storage structure to store a reference to the code line in response to an update to an Instruction Dispatch Queue (IDQ). Logic circuitry controls additional code line fetch operations based at least in part on a comparison of a number of ongoing speculative code fetches and a determination that the code line is speculative. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220197794A1

公开(公告)日：2022-06-23

申请号：US17130698

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Prathmesh Kallurkar ,  Anant Vithal Nori ,  Sreenivas Subramoney

IPC: G06F12/084 ,  G06F12/0811 ,  G06F9/50

Abstract: An embodiment of an integrated circuit may comprise a core, a first level core cache memory coupled to the core, a shared core cache memory coupled to the core, a first cache controller coupled to the core and communicatively coupled to the first level core cache memory, a second cache controller coupled to the core and communicatively coupled to the shared core cache memory, and circuitry coupled to the core and communicatively coupled to the first cache controller and the second cache controller to determine if a workload has a large code footprint, and, if so determined, partition N ways of the shared core cache memory into first and second chunks of ways with the first chunk of M ways reserved for code cache lines from the workload and the second chunk of N minus M ways reserved for data cache lines from the workload, where N and M are positive integer values and N minus M is greater than zero. Other embodiments are disclosed and claimed.

公开(公告)号：US12066945B2

公开(公告)日：2024-08-20

申请号：US17130698

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Prathmesh Kallurkar ,  Anant Vithal Nori ,  Sreenivas Subramoney

IPC: G06F12/084 ,  G06F9/50 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0871

CPC classification number: G06F12/084 ,  G06F9/5016 ,  G06F12/0811 ,  G06F12/0848 ,  G06F12/0871

Abstract: An embodiment of an integrated circuit may comprise a core, a first level core cache memory coupled to the core, a shared core cache memory coupled to the core, a first cache controller coupled to the core and communicatively coupled to the first level core cache memory, a second cache controller coupled to the core and communicatively coupled to the shared core cache memory, and circuitry coupled to the core and communicatively coupled to the first cache controller and the second cache controller to determine if a workload has a large code footprint, and, if so determined, partition N ways of the shared core cache memory into first and second chunks of ways with the first chunk of M ways reserved for code cache lines from the workload and the second chunk of N minus M ways reserved for data cache lines from the workload, where N and M are positive integer values and N minus M is greater than zero. Other embodiments are disclosed and claimed.

公开(公告)号：US11847053B2

公开(公告)日：2023-12-19

申请号：US16833419

申请日：2020-03-27

Applicant: INTEL CORPORATION

Inventor： Prathmesh Kallurkar ,  Anant Vithal Nori ,  Sreenivas Subramoney

IPC: G06F12/08 ,  G06F12/12 ,  G06F11/30 ,  G06F9/30 ,  G06F12/0811 ,  G06F12/123

CPC classification number: G06F12/0811 ,  G06F9/30047 ,  G06F11/3037 ,  G06F12/123 ,  G06F2212/1021

Abstract: Systems, methods, and apparatuses relating to circuitry to implement a duplication resistant on-die irregular data prefetcher are described. In one embodiment, a hardware processor includes a cache to store a plurality of cache lines of data, a processing element to execute instructions to generate memory requests, and a prefetch circuit to track a first set of cache lines, requested to be accessed by the memory requests, that repeat in a first number of executed instructions, track a second set of cache lines, requested to be accessed by the memory requests, that repeat in a second, larger number of executed instructions, detect a memory request from an instruction for a cache line from the cache, determine if the cache line is within the first set of cache lines or the second set of cache lines, update first correlation data for the cache line when the cache line is within the first set of cache lines, and update second correlation data for the cache line when the cache line is within the second set of cache lines.

公开(公告)号：US20230185718A1

公开(公告)日：2023-06-15

申请号：US17551172

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Anant Vithal Nori ,  Prathmesh Kallurkar ,  Niranjan Kumar Soundararajan ,  Sreenivas Subramoney ,  Lihu Rappoport ,  Hanna Alam ,  Adrian Moga ,  Ronak Singhal

IPC: G06F12/084

CPC classification number: G06F12/084 ,  G06F2212/62

Abstract: Methods and apparatus relating to de-prioritizing speculative code lines in on-chip caches are described. In an embodiment, logic circuitry determines whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache. The logic circuitry causes de-prioritization of a code line, corresponding to the code miss request, in the shared cache in response to an absence of the reference in the storage structure. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210303468A1

公开(公告)日：2021-09-30

申请号：US16833419

申请日：2020-03-27

Applicant: INTEL CORPORATION

Inventor： Prathmesh Kallurkar ,  Anant Vithal Nori ,  Sreenivas Subramoney

IPC: G06F12/0811 ,  G06F12/123 ,  G06F9/30 ,  G06F11/30

Abstract: Systems, methods, and apparatuses relating to circuitry to implement a duplication resistant on-die irregular data prefetcher are described. In one embodiment, a hardware processor includes a cache to store a plurality of cache lines of data, a processing element to execute instructions to generate memory requests, and a prefetch circuit to track a first set of cache lines, requested to be accessed by the memory requests, that repeat in a first number of executed instructions, track a second set of cache lines, requested to be accessed by the memory requests, that repeat in a second, larger number of executed instructions, detect a memory request from an instruction for a cache line from the cache, determine if the cache line is within the first set of cache lines or the second set of cache lines, update first correlation data for the cache line when the cache line is within the first set of cache lines, and update second correlation data for the cache line when the cache line is within the second set of cache lines.