公开(公告)号：US11720364B2

公开(公告)日：2023-08-08

申请号：US17033282

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Hanna Alam ,  Leeor Peled ,  Refael Mizrahi ,  Amir Leibovitz ,  Jonathan Beimel ,  James Hermerding, II ,  Gilad Olswang ,  Michal Moran ,  Moran Peri ,  Ido Karavany ,  Sudheer Nair ,  Hadas Beja ,  Avishai Wagner ,  Ronen Laperdon

IPC: G06F9/38 ,  G06F9/30 ,  G06F11/30 ,  G06F9/50

CPC classification number: G06F9/3802 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/505 ,  G06F11/3024

Abstract: Disclosed Methods, Apparatus, and articles of manufacture to dynamically enable and/or disable prefetchers are disclosed. An example apparatus include an interface to access telemetry data, the telemetry data corresponding to a counter of a core in a central processing unit, the counter corresponding to a first phase of a workload executed at the central processing unit; a prefetcher state selector to select a prefetcher state for a subsequent phase based on the telemetry data; and the interface to instruct the core in the central processing unit to operate in the subsequent phase according to the prefetcher state.

公开(公告)号：US20230315630A1

公开(公告)日：2023-10-05

申请号：US17708435

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Hanna Alam ,  Yuval Bustan ,  Tomer Exterman ,  Dor Kahana ,  Larisa Novakovsky ,  Joseph Nuzman

IPC: G06F12/0811

CPC classification number: G06F12/0811 ,  G06F2212/62

Abstract: Methods and apparatus relating to a dynamic inclusive and non-inclusive caching policy are described. In an embodiment, a first cache has a higher level than a second cache. Circuitry determines a caching policy between the first cache and the second cache based on a comparison of a number of active processor cores and a threshold value. The caching policy is one of an inclusive caching policy or a non-inclusive caching policy. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190138451A1

公开(公告)日：2019-05-09

申请号：US16235276

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Hanna Alam ,  Joseph Nuzman

IPC: G06F12/0862 ,  G06F12/0877

Abstract: Disclosed embodiments relate to systems and methods structured to predict and prefetch a cache access based on a delta pattern. In one example, a processor is structured to extract a delta history corresponding to a delta pattern and a current page, generate a bucketed delta history based on the delta history corresponding to the current page, select a prediction entry based on the bucketed delta history, generate one or more prefetch candidates based on a confidence threshold, the confidence threshold structured to indicate one or more probable delta patterns, and filter the one or more prefetch candidates.

公开(公告)号：US12019553B2

公开(公告)日：2024-06-25

申请号：US17130696

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Hanna Alam ,  Joseph Nuzman

IPC: G06F12/0862 ,  G06F12/084

CPC classification number: G06F12/0862 ,  G06F12/084 ,  G06F2212/6028

Abstract: In one embodiment, a processor includes: one or more execution circuits to execute instructions; a stream prediction circuit coupled to the one or more execution circuits, the stream prediction circuit to receive demand requests for information and, based at least in part on the demand requests, generate a page prefetch hint for a first page; and a prefetcher circuit to generate first prefetch requests each for a cache line, the stream prediction circuit decoupled from the prefetcher circuit. Other embodiments are described and claimed.

公开(公告)号：US20230185718A1

公开(公告)日：2023-06-15

申请号：US17551172

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Anant Vithal Nori ,  Prathmesh Kallurkar ,  Niranjan Kumar Soundararajan ,  Sreenivas Subramoney ,  Lihu Rappoport ,  Hanna Alam ,  Adrian Moga ,  Ronak Singhal

IPC: G06F12/084

CPC classification number: G06F12/084 ,  G06F2212/62

Abstract: Methods and apparatus relating to de-prioritizing speculative code lines in on-chip caches are described. In an embodiment, logic circuitry determines whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache. The logic circuitry causes de-prioritization of a code line, corresponding to the code miss request, in the shared cache in response to an absence of the reference in the storage structure. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230091205A1

公开(公告)日：2023-03-23

申请号：US17479582

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Adrian Moga ,  Ugonna Echeruo ,  Eduard Roytman ,  Krishnakanth Sistla ,  Joseph Nuzman ,  Brinda Ganesh ,  Meenakshisundaram Chinthamani ,  Yen-Cheng Liu ,  Sai Prashanth Muralidhara ,  Vivek Kozhikkottu ,  Hanna Alam ,  Narasimha Sridhar Srirangam

IPC: G06F12/0862 ,  G06F13/28

Abstract: Methods and apparatus relating to memory side prefetch architecture for improved memory bandwidth are described. In an embodiment, logic circuitry transmits a Direct Memory Controller Prefetch (DMCP) request to cause a prefetch of data from memory. A memory controller receives the DMCP request and issues a plurality of read operations to the memory in response to the DMCP request. Data read from the memory is stored in a storage structure in response to the plurality of read operations. Other embodiments are also disclosed and claimed.

公开(公告)号：US11249909B2

公开(公告)日：2022-02-15

申请号：US16235276

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Hanna Alam ,  Joseph Nuzman

IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0897

Abstract: Systems and methods to predict and prefetch a cache access based on a delta pattern are disclosed. The delta pattern may comprise a sequence of differences between first and second cache accesses within a page. In one example, a processor includes execution circuitry to extract a delta history corresponding to a delta pattern associated with one or more previous cache accesses corresponding to a page of memory. The processor execution circuitry further generates a bucketed delta history based on the delta history corresponding to the page of memory and selects a prediction entry based on the bucketed delta history. The processor execution circuitry then identifies one or more prefetch candidates based on a confidence threshold, with the confidence threshold indicating one or more probable delta patterns, and filters the one or more prefetch candidates. Prefetch circuitry of the processor then predicts and prefetches a cache access based the one or more prefetch candidates.