公开(公告)号：US20230099540A1

公开(公告)日：2023-03-30

申请号：US17485294

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Sarah ATANASOV ,  Rahul RAMAMURTHY ,  Seung Hoon SUNG

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a semiconductor device comprises a sub-fin. In an embodiment, the sub-fin comprises a semiconductor material. In an embodiment, a channel is above the sub-fin, where the channel is physically detached from the sub-fin. In an embodiment a first layer is over the sub-fin, and a second layer is over the first layer. In an embodiment, the second layer is different than the first layer.

公开(公告)号：US20230100505A1

公开(公告)日：2023-03-30

申请号：US17485238

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Ashish Verma PENUMATCHA ,  Sarah ATANASOV ,  Seung Hoon SUNG ,  Rahul RAMAMURTHY ,  I-Cheng TUNG ,  Uygar E. AVCI ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Chia-Ching LIN ,  Kaan OGUZ

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66

Abstract: Embodiments disclosed herein include transistor devices and methods of forming such devices. In an embodiment, a transistor device comprises a first channel, wherein the first channel comprises a semiconductor material and a second channel above the first channel, wherein the second channel comprises the semiconductor material. In an embodiment, a first spacer is between the first channel and the second channel, and a second spacer is between the first channel and the second channel. In an embodiment, a first gate dielectric is over a surface of the first channel that faces the second channel, and a second gate dielectric is over a surface of the second channel that faces the first channel. In an embodiment, the first gate dielectric is physically separated from the second gate dielectric.

公开(公告)号：US20230111323A1

公开(公告)日：2023-04-13

申请号：US17485325

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Rahul RAMAMURTHY ,  Ashish Verma PENUMATCHA ,  Sarah ATANASOV ,  Seung Hoon SUNG ,  Inanc MERIC ,  Uygar E. AVCI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/225

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to minimizing sub channel leakage within stacked GAA nanosheet transistors by doping an oxide layer on top of the sub channel. In embodiments, this doping may include selective introduction of charge species, for example carbon, within the gate oxide layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20230100952A1

公开(公告)日：2023-03-30

申请号：US17485291

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： I-Cheng TUNG ,  Ashish Verma PENUMATCHA ,  Seung Hoon SUNG ,  Sarah ATANASOV ,  Jack T. KAVALIEROS ,  Matther V. METZ ,  Uygar E. AVCI ,  Rahul RAMAMURTHY ,  Chia-Ching LIN ,  Kaan OGUZ

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: Embodiments disclosed herein include transistors and transistor gate stacks. In an embodiment, a transistor gate stack comprises a semiconductor channel. In an embodiment, an interlayer (IL) is over the semiconductor channel. In an embodiment, the IL has a thickness of 1 nm or less and comprises zirconium. In an embodiment, a gate dielectric is over the IL, and a gate metal over the gate dielectric.