公开(公告)号：US20210406060A1

公开(公告)日：2021-12-30

申请号：US16912770

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Monica Gupta ,  Eliezer Weissmann ,  Hisham Abu Salah ,  Rajshree Arun Chabukswar ,  Russell Jerome Fenger ,  Eugene Gorbatov ,  Guruprasad Settuvalli ,  Balaji Masanamuthu Chinnathurai ,  Sumant Tapas ,  Meghana Gudaram ,  Raj Kumar Subramaniam

IPC: G06F9/48 ,  G06F1/28 ,  G06F9/4401

Abstract: A data processing system comprises a hybrid processor comprising a big TPU and a small TPU. At least one of the TPUs comprises an LP of a processing core that supports SMT. The hybrid processor further comprises hardware feedback circuitry. A machine-readable medium in the data processing system comprises instructions which, when executed, enable an OS in the data processing system to collect (a) processor topology data from the hybrid processor and (b) hardware feedback for at least one of the TPUs from the hardware feedback circuitry. The instructions also enable the OS to respond to a determination that a thread is ready to be scheduled by utilizing (a) an OP setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread. Other embodiments are described and claimed.

公开(公告)号：US11531563B2

公开(公告)日：2022-12-20

申请号：US16912770

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Monica Gupta ,  Eliezer Weissmann ,  Hisham Abu Salah ,  Rajshree Arun Chabukswar ,  Russell Jerome Fenger ,  Eugene Gorbatov ,  Guruprasad Settuvalli ,  Balaji Masanamuthu Chinnathurai ,  Sumant Tapas ,  Meghana Gudaram ,  Raj Kumar Subramaniam

IPC: G06F9/48 ,  G06F1/28 ,  G06F9/4401

Abstract: A data processing system comprises a hybrid processor comprising a big TPU and a small TPU. At least one of the TPUs comprises an LP of a processing core that supports SMT. The hybrid processor further comprises hardware feedback circuitry. A machine-readable medium in the data processing system comprises instructions which, when executed, enable an OS in the data processing system to collect (a) processor topology data from the hybrid processor and (b) hardware feedback for at least one of the TPUs from the hardware feedback circuitry. The instructions also enable the OS to respond to a determination that a thread is ready to be scheduled by utilizing (a) an OP setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread. Other embodiments are described and claimed.