公开(公告)号：US20250113430A1

公开(公告)日：2025-04-03

申请号：US18513045

申请日：2023-11-17

Applicant: Intel Corporation

Inventor： Venkata Mahesh Gunnam ,  Rakesh Yedri ,  Phani Alaparthi ,  David Elayaraj Samaraj ,  Jackson C.P. Kong ,  Bala Subramanya ,  Navneet Kumar Singh ,  Yagnesh V. Waghela

IPC: H05K1/02 ,  H05K3/12 ,  H05K3/34

Abstract: Technologies for reducing the impact of inductors on electrical traces are disclosed. In an illustrative embodiment, conductive ink is applied in a silk screen layer on top of a solder mask of a circuit board. The conductive ink forms shield regions under and near where inductors are placed and/or where a power plane is routed. The conductive shield regions may be coupled to a ground plane in the circuit board. The conductive shield regions can partially shield traces under and near the inductor, reducing the noise induced on nearby traces. The conductive shield regions can allow traces for high-speed input/output signals to be routed closer to the inductor, reducing the size, number of layers, and/or cost of the circuit board. In some embodiments, the conductive shield regions can shield emissions from the power plane, reducing interference on antennas of a device.