公开(公告)号：US20210191490A1

公开(公告)日：2021-06-24

申请号：US17191564

申请日：2021-03-03

Applicant: Intel Corporation

Inventor： Phani Kumar KANDULA ,  Eric J. DEHAEMER ,  Dorit SHAPIRA ,  Ramkumar NAGAPPAN ,  Vivek GARG ,  Fuat KECELI ,  Mani PRAKASH ,  David C. HOLCOMB ,  Horthense D. TAMDEM ,  Olivier FRANZA ,  Vjekoslav SVILAN

IPC: G06F1/324

Abstract: Methods and apparatus for balancing power between discrete components, such as processing units (e.g., CPUs) and accelerators in a compute node or platform. Power consumption of the compute platform is monitored to detect for conditions under which a threshold (e.g., power supply capacity threshold) is exceeded. In response, the operating frequencies of a processing unit and/or other platform components such as accelerators, are adjusted to reduce the power consumption of the platform to return below the threshold. Power limit biasing hints (scaling weights) are provided to platform components, along with a power violation index, which are used to adjust the operating frequencies of the platform components. Optionally, a processing unit can calculate the power violation index and the scaling weights and directly control the frequencies of itself and platform components. Embodiments of multi-socket platforms are also provided.