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公开(公告)号:US20200241980A1
公开(公告)日:2020-07-30
申请号:US16779152
申请日:2020-01-31
Applicant: Intel Corporation
Inventor: Eric J. DeHaemer , Arijit Biswas , Reid J. Riedlinger , Ian M. Steiner
IPC: G06F11/20
Abstract: A multicore processor may include multiple processing cores that were previously designated as active cores and at least one processing core that was previously designated as a functional spare. The processor may include an interface to receive, during operation of the processor in an end-user environment, a request to change the designation of at least one of the processing cores. The processor may be to store, into a desired cores configuration data structure in response to the request, data representing a bitmask that reflects the requested change, and to execute a reset sequence. During the reset sequence, the processor may activate, dependent on the bitmask, a processing core previously designated as a functional spare, or may deactivate, dependent on the bitmask, a processing core previously designated as an active core. The processor may include a predetermined maximum number of active cores and a predetermined minimum number of functional spares.
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公开(公告)号:US20180181474A1
公开(公告)日:2018-06-28
申请号:US15388146
申请日:2016-12-22
Applicant: Intel Corporation
Inventor: Eric J. DeHaemer , Arijit Biswas , Reid J. Riedlinger , Ian M. Steiner
IPC: G06F11/20
CPC classification number: G06F11/2028 , G06F11/2041 , G06F11/2043
Abstract: A multicore processor may include multiple processing cores that were previously designated as active cores and at least one processing core that was previously designated as a functional spare. The processor may include an interface to receive, during operation of the processor in an end-user environment, a request to change the designation of at least one of the processing cores. The processor may be to store, into a desired cores configuration data structure in response to the request, data representing a bitmask that reflects the requested change, and to execute a reset sequence. During the reset sequence, the processor may activate, dependent on the bitmask, a processing core previously designated as a functional spare, or may deactivate, dependent on the bitmask, a processing core previously designated as an active core. The processor may include a predetermined maximum number of active cores and a predetermined minimum number of functional spares.
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公开(公告)号:US10552270B2
公开(公告)日:2020-02-04
申请号:US15388146
申请日:2016-12-22
Applicant: Intel Corporation
Inventor: Eric J. DeHaemer , Arijit Biswas , Reid J. Riedlinger , Ian M. Steiner
Abstract: A multicore processor may include multiple processing cores that were previously designated as active cores and at least one processing core that was previously designated as a functional spare. The processor may include an interface to receive, during operation of the processor in an end-user environment, a request to change the designation of at least one of the processing cores. The processor may be to store, into a desired cores configuration data structure in response to the request, data representing a bitmask that reflects the requested change, and to execute a reset sequence. During the reset sequence, the processor may activate, dependent on the bitmask, a processing core previously designated as a functional spare, or may deactivate, dependent on the bitmask, a processing core previously designated as an active core. The processor may include a predetermined maximum number of active cores and a predetermined minimum number of functional spares.
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