Flexible byzantine fault tolerance

    公开(公告)号:US11809288B2

    公开(公告)日:2023-11-07

    申请号:US17746066

    申请日:2022-05-17

    Applicant: VMware, Inc.

    CPC classification number: G06F11/187 G06F11/1425 G06F11/182 G06F11/2041

    Abstract: A method and system for performing a flexible Byzantine fault tolerant (BFT) protocol. The method includes sending, from a client device, a proposed value to a plurality of replica devices and receiving, from at least one of the plurality of replica devices, a safe vote on the proposed value. The replica device sends the safe vote, based on a first quorum being reached, to the client device and each of the other replica devices of the plurality of replica devices. The method further includes determining that a number of received safe votes for the proposed value meets or exceeds a second quorum threshold, selecting the proposed value based on the determination, and setting a period of time within which to receive additional votes. The method further includes, based on the period of time elapsing without receiving the additional votes, committing the selected value for the single view.

    ROW REPAIR AND ACCURACY IMPROVEMENTS IN ANALOG COMPUTE-IN-MEMORY ARCHITECTURES

    公开(公告)号:US20230251943A1

    公开(公告)日:2023-08-10

    申请号:US18298906

    申请日:2023-04-11

    CPC classification number: G06F11/2041

    Abstract: Systems, apparatuses and methods may provide for technology that includes a plurality of analog to digital converters (ADCs), compute-in-memory (CiM) multiply-accumulate (MAC) hardware coupled to the plurality of ADCs, and a plurality of digital to analog converters (DACs) coupled to the CiM MAC hardware, wherein the plurality of DACs includes one or more redundant DACs. In one example, the technology uses a DAC disconnect scheme to statically bypass defective memory bitcells and compute capacitors to improve yield with minimal overhead, and dynamically boost the effective precision of the ADC in the presence of weight/activation sparsity in neural network (NN) compute.

    Systems and Methods for In-Field Core Failover

    公开(公告)号:US20180181474A1

    公开(公告)日:2018-06-28

    申请号:US15388146

    申请日:2016-12-22

    CPC classification number: G06F11/2028 G06F11/2041 G06F11/2043

    Abstract: A multicore processor may include multiple processing cores that were previously designated as active cores and at least one processing core that was previously designated as a functional spare. The processor may include an interface to receive, during operation of the processor in an end-user environment, a request to change the designation of at least one of the processing cores. The processor may be to store, into a desired cores configuration data structure in response to the request, data representing a bitmask that reflects the requested change, and to execute a reset sequence. During the reset sequence, the processor may activate, dependent on the bitmask, a processing core previously designated as a functional spare, or may deactivate, dependent on the bitmask, a processing core previously designated as an active core. The processor may include a predetermined maximum number of active cores and a predetermined minimum number of functional spares.

Patent Agency Ranking