公开(公告)号：US10552270B2

公开(公告)日：2020-02-04

申请号：US15388146

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： Eric J. DeHaemer ,  Arijit Biswas ,  Reid J. Riedlinger ,  Ian M. Steiner

IPC: G06F11/00 ,  G06F11/20

Abstract: A multicore processor may include multiple processing cores that were previously designated as active cores and at least one processing core that was previously designated as a functional spare. The processor may include an interface to receive, during operation of the processor in an end-user environment, a request to change the designation of at least one of the processing cores. The processor may be to store, into a desired cores configuration data structure in response to the request, data representing a bitmask that reflects the requested change, and to execute a reset sequence. During the reset sequence, the processor may activate, dependent on the bitmask, a processing core previously designated as a functional spare, or may deactivate, dependent on the bitmask, a processing core previously designated as an active core. The processor may include a predetermined maximum number of active cores and a predetermined minimum number of functional spares.

公开(公告)号：US20230131521A1

公开(公告)日：2023-04-27

申请号：US18086799

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F1/3203 ,  G06F9/50 ,  G06F1/324

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US11953962B2

公开(公告)日：2024-04-09

申请号：US18086799

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F9/50 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/52 ,  G06F13/20 ,  G06F1/3287 ,  G06F1/3296

CPC classification number: G06F1/3203 ,  G06F1/28 ,  G06F1/324 ,  G06F9/5044 ,  G06F9/5094 ,  G06F9/52 ,  G06F13/20 ,  G06F1/3287 ,  G06F1/3296

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US20200241980A1

公开(公告)日：2020-07-30

申请号：US16779152

申请日：2020-01-31

Applicant: Intel Corporation

Inventor： Eric J. DeHaemer ,  Arijit Biswas ,  Reid J. Riedlinger ,  Ian M. Steiner

IPC: G06F11/20

Abstract: A multicore processor may include multiple processing cores that were previously designated as active cores and at least one processing core that was previously designated as a functional spare. The processor may include an interface to receive, during operation of the processor in an end-user environment, a request to change the designation of at least one of the processing cores. The processor may be to store, into a desired cores configuration data structure in response to the request, data representing a bitmask that reflects the requested change, and to execute a reset sequence. During the reset sequence, the processor may activate, dependent on the bitmask, a processing core previously designated as a functional spare, or may deactivate, dependent on the bitmask, a processing core previously designated as an active core. The processor may include a predetermined maximum number of active cores and a predetermined minimum number of functional spares.

公开(公告)号：US11579944B2

公开(公告)日：2023-02-14

申请号：US16190806

申请日：2018-11-14

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F9/50 ,  G06F9/52 ,  G06F13/20 ,  G06F1/28 ,  G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  G06F1/3287

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US20190079806A1

公开(公告)日：2019-03-14

申请号：US16190806

申请日：2018-11-14

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F9/52 ,  G06F13/20 ,  G06F9/50 ,  G06F1/28

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US20180181474A1

公开(公告)日：2018-06-28

申请号：US15388146

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： Eric J. DeHaemer ,  Arijit Biswas ,  Reid J. Riedlinger ,  Ian M. Steiner

IPC: G06F11/20

CPC classification number: G06F11/2028 ,  G06F11/2041 ,  G06F11/2043

Abstract: A multicore processor may include multiple processing cores that were previously designated as active cores and at least one processing core that was previously designated as a functional spare. The processor may include an interface to receive, during operation of the processor in an end-user environment, a request to change the designation of at least one of the processing cores. The processor may be to store, into a desired cores configuration data structure in response to the request, data representing a bitmask that reflects the requested change, and to execute a reset sequence. During the reset sequence, the processor may activate, dependent on the bitmask, a processing core previously designated as a functional spare, or may deactivate, dependent on the bitmask, a processing core previously designated as an active core. The processor may include a predetermined maximum number of active cores and a predetermined minimum number of functional spares.