公开(公告)号：US20190220413A1

公开(公告)日：2019-07-18

申请号：US16361512

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Rupin H. Vakharwala ,  Paula Petrica

IPC: G06F12/0862 ,  G06F12/1036 ,  G06F13/42

CPC classification number: G06F12/0862 ,  G06F12/1036 ,  G06F13/42 ,  G06F2213/0026

Abstract: Systems, methods, and devices can include circuitry or computer program products to receive a memory address translation request message from a downstream connected device; identify, from the memory address translation request message, a permission indication that the device intends to perform a write access to one or more memory address locations specified in the memory address translation request message; identify, from an address translation and protection table (ATPT), a dirty bit value associated with the one or more memory address locations; and transmit a translation of the one or more memory address locations and a read or read+write permission to the device based on the permission indication in the memory address translation request message and the dirty bit.

公开(公告)号：US11126554B2

公开(公告)日：2021-09-21

申请号：US16361512

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Rupin H. Vakharwala ,  Paula Petrica

IPC: G06F12/00 ,  G06F12/0862 ,  G06F13/42 ,  G06F12/1036

Abstract: Systems, methods, and devices can include circuitry or computer program products to receive a memory address translation request message from a downstream connected device; identify, from the memory address translation request message, a permission indication that the device intends to perform a write access to one or more memory address locations specified in the memory address translation request message; identify, from an address translation and protection table (ATPT), a dirty bit value associated with the one or more memory address locations; and transmit a translation of the one or more memory address locations and a read or read+write permission to the device based on the permission indication in the memory address translation request message and the dirty bit.

公开(公告)号：US20240126702A1

公开(公告)日：2024-04-18

申请号：US17949803

申请日：2022-09-21

Applicant: Intel Corporation

Inventor： Mark Dechene ,  Ryan Carlson ,  Sudeepto Majumdar ,  Rafael Trapani Possignolo ,  Paula Petrica ,  Richard Klass ,  Meenakshi Marathe

IPC: G06F12/1027 ,  G06F12/0882

CPC classification number: G06F12/1027 ,  G06F12/0882 ,  G06F2212/1021

Abstract: Techniques for slicing memory of a hardware processor core by linear address are described. In certain examples, a hardware processor core includes memory circuitry having: a cache comprising a plurality of slices of memory, wherein each of a plurality of cache lines of memory are only stored in a single slice, and each slice stores a different range of address values compared to any other slice, wherein each of the plurality of slices of memory comprises: an incomplete load buffer to store a load address from the address generation circuit for a load request operation, broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, in response to the load address being within a range of address values of that memory slice, a store address buffer to store a store address from the address generation circuit for a store request operation, broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, in response to the store address being within a range of address values of that memory slice, a store data buffer to store data, including the data for the store request operation that is to be stored at the store address, for each store request operation broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, and a store completion buffer to store the data for the store request operation in response to the store address being stored in the store address buffer of that memory slice, and, in response, clear the store address for the store request operation from the store address buffer and clear the data for the store request operation from the store data buffer.