公开(公告)号：US20220114115A1

公开(公告)日：2022-04-14

申请号：US17557963

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Anand K. Enamandram ,  Rita Deepak Gupta ,  Robert A. Branch ,  Kerry Vander Kamp

IPC: G06F13/16

Abstract: An apparatus comprising a first memory interface of a first type to couple to at least one first memory device; a second memory interface of a second type to couple to at least one second memory device; and circuitry to interleave memory requests targeting contiguous memory addresses among the at least one first memory device and the at least one second memory device.

公开(公告)号：US20220004488A1

公开(公告)日：2022-01-06

申请号：US17482304

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Barun Bikash Paul ,  Rita Deepak Gupta ,  Suresh Thirumandas

IPC: G06F12/02 ,  G06F12/1081 ,  G06F12/06

Abstract: The apparatus of a disaggregated memory architecture (DMA) including a shared memory and multiple nodes is programmable by a primary node of the DMA. The primary node executes a programming agent to, prior to memory access requests to access the shared memory, cause a programming of register entries of one or more registers of a memory pooling circuitry (MPC) with information to be used by a decoder of the MPC to translate host physical addresses (HPA) of memory access requests of the nodes to local memory addresses (LMAs). The LMAs are to be processed by one or more memory controllers (MCs) coupled to the one or more registers based on MC memory regions in each of the one or more MCs, the MC memory regions having a predetermined memory size granularity. At least some of the LMAs map to non-contiguous memory regions of the shared memory and of the one or more MCs.