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    CLUSTER IDENTIFIER REMAPPING FOR ASYMMETRIC TOPOLOGIES
    1.
    发明申请
    CLUSTER IDENTIFIER REMAPPING FOR ASYMMETRIC TOPOLOGIES 有权

    公开(公告)号：US20220004439A1

    公开(公告)日：2022-01-06

    申请号：US17477470

    申请日：2021-09-16

    Applicant: Intel Corporation

    Inventor： Vinit Mathew Abraham ,  Anand K. Enamandram ,  Eswaramoorthi Nallusamy

    IPC: G06F9/50 ,  G06F9/30 ,  G06F9/4401 ,  G06F13/42

    Abstract: A first plurality of integrated circuit blocks of a first chip are connected to a second plurality of integrated circuit blocks of a second chip. A cluster remapping table is provided on the second chip and is to be programmed to identify a desired asymmetric topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks. Logic is to discover the actual topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks and determine whether the actual topology matches the desired topology as described in the cluster remapping table.

    Cluster identifier remapping for asymmetric topologies
    2.
    发明授权
    Cluster identifier remapping for asymmetric topologies 有权

    公开(公告)号：US12271760B2

    公开(公告)日：2025-04-08

    申请号：US17477470

    申请日：2021-09-16

    Applicant: Intel Corporation

    Inventor： Vinit Mathew Abraham ,  Anand K. Enamandram ,  Eswaramoorthi Nallusamy

    IPC: G06F9/50 ,  G06F9/30 ,  G06F9/4401 ,  G06F13/42

    Abstract: A first plurality of integrated circuit blocks of a first chip are connected to a second plurality of integrated circuit blocks of a second chip. A cluster remapping table is provided on the second chip and is to be programmed to identify a desired asymmetric topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks. Logic is to discover the actual topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks and determine whether the actual topology matches the desired topology as described in the cluster remapping table.

    ACCESSING A MEMORY USING INDEX OFFSET INFORMATION
    3.
    发明公开
    ACCESSING A MEMORY USING INDEX OFFSET INFORMATION 审中-公开

    公开(公告)号：US20230195616A1

    公开(公告)日：2023-06-22

    申请号：US17553458

    申请日：2021-12-16

    Applicant: Intel Corporation

    Inventor： Monam Agarwal ,  Anand K. Enamandram ,  Wei Chen ,  Kerry Vander Kamp ,  Robert A. Branch ,  Yen-Cheng Liu

    IPC: G06F13/16 ,  G06F12/02

    CPC classification number: G06F13/161 ,  G06F12/0238 ,  G06F12/0292 ,  G06F13/1642 ,  G06F13/1668 ,  G06F2212/1021

    Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

    FLEXIBLE PROVISIONING OF COHERENT MEMORY ADDRESS DECODERS IN HARDWARE
    5.
    发明公开
    FLEXIBLE PROVISIONING OF COHERENT MEMORY ADDRESS DECODERS IN HARDWARE 审中-公开

    公开(公告)号：US20230367492A1

    公开(公告)日：2023-11-16

    申请号：US17741386

    申请日：2022-05-10

    Applicant: Intel Corporation

    Inventor： Ritu Gupta ,  Anand K. Enamandram

    IPC: G06F3/06

    CPC classification number: G06F3/0629 ,  G06F3/0611 ,  G06F3/0673

    Abstract: Embodiments of apparatuses, methods, and systems for flexible provisioning of coherent memory address decoders in hardware are disclosed. In an embodiment, an apparatus includes a plurality of address decoders and a plurality of configuration storage locations. Each of the configuration storage locations corresponds to one of the plurality of address decoders to configure the corresponding one of the plurality of address decoders to decode based on a corresponding one of a plurality of decode rules. Each of the plurality of configuration storage locations is allocated to one of a plurality of memory tiers.

    SCALABLE ADDRESS DECODING SCHEME FOR CXL TYPE-2 DEVICES WITH PROGRAMMABLE INTERLEAVE GRANULARITY
    6.
    发明申请
    SCALABLE ADDRESS DECODING SCHEME FOR CXL TYPE-2 DEVICES WITH PROGRAMMABLE INTERLEAVE GRANULARITY 有权

    公开(公告)号：US20230086222A1

    公开(公告)日：2023-03-23

    申请号：US17478828

    申请日：2021-09-17

    Applicant: Intel Corporation

    Inventor： Anand K. Enamandram ,  Ritu Gupta

    IPC: G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  G06F13/16 ,  G06F9/46

    Abstract: Methods and apparatus relating to a scalable address decoding scheme for Compute Express Link™ or CXL™ Type-2 devices with programmable interleave granularity are described. In an embodiment, configurator logic circuitry determines an interleave granularity and an address range size for a plurality of devices coupled to a socket of a processor. A single System Address Decoder (SAD) rule for two or more of the plurality of the devices coupled to the socket of the processor is stored in memory. A memory access transaction directed at a first device from the plurality of devices is routed to the first device in accordance with the SAD rule. Other embodiments are also disclosed and claimed.

    Accessing a memory using index offset information
    9.
    发明授权
    Accessing a memory using index offset information 有权

    公开(公告)号：US11860670B2

    公开(公告)日：2024-01-02

    申请号：US17553458

    申请日：2021-12-16

    Applicant: Intel Corporation

    Inventor： Monam Agarwal ,  Anand K. Enamandram ,  Wei Chen ,  Kerry Vander Kamp ,  Robert A. Branch ,  Yen-Cheng Liu

    IPC: G06F12/02 ,  G06F13/16

    CPC classification number: G06F12/0292 ,  G06F12/0238 ,  G06F13/161 ,  G06F13/1642 ,  G06F13/1668 ,  G06F2212/1021

    Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

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