公开(公告)号：US20220004351A1

公开(公告)日：2022-01-06

申请号：US17481572

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Aswin Padmanabhan ,  Sangeeta Ghangam Manepalli ,  Kiran K. Velicheti ,  Robert James Johnston ,  Chandra Konduru ,  Todd M. Witter

IPC: G06F3/14 ,  H04N5/05

Abstract: In one embodiment, a processing device includes a plurality of display interfaces, a plurality of display controllers, and display synchronization circuitry. The display interfaces are used to interface with a plurality of display devices, and the display controllers are used to output video frames to the display devices via the display interfaces. Moreover, the display synchronization circuitry includes a clock synchronization interface and a frame synchronization interface. The clock synchronization interface is used to synchronize a clock rate across the display controllers, while the frame synchronization interface is used to synchronize a frame rate across the display controllers.

公开(公告)号：US12124759B2

公开(公告)日：2024-10-22

申请号：US17481572

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Aswin Padmanabhan ,  Sangeeta Ghangam Manepalli ,  Kiran K. Velicheti ,  Robert James Johnston ,  Chandra Konduru ,  Todd M. Witter

IPC: G06F3/14

CPC classification number: G06F3/1446

Abstract: In one embodiment, a processing device includes a plurality of display interfaces, a plurality of display controllers, and display synchronization circuitry. The display interfaces are used to interface with a plurality of display devices, and the display controllers are used to output video frames to the display devices via the display interfaces. Moreover, the display synchronization circuitry includes a clock synchronization interface and a frame synchronization interface. The clock synchronization interface is used to synchronize a clock rate across the display controllers, while the frame synchronization interface is used to synchronize a frame rate across the display controllers.