公开(公告)号：US20230253814A1

公开(公告)日：2023-08-10

申请号：US17592741

申请日：2022-02-04

Applicant: Intel Corporation

Inventor： Jagadish V. Singh ,  Raghavendra Rao ,  Rohit Parakkal ,  Anoop Parchuru

IPC: H02J7/00 ,  H02M3/155

CPC classification number: H02J7/007182 ,  H02M3/155

Abstract: Systems, apparatuses, and methods may provide for power delivery circuit technology that includes a charger controller coupled to a battery output and an intermediate bus converter coupled to an adapter output, a system power input and the battery output, wherein the intermediate bus converter varies a voltage level of the system power input based on the battery output. In one example, the voltage level of the system power input is one or more of a percentage value or an absolute value greater than a voltage level of the battery output. Additionally, the charger controller may connect the battery output to the system power input in response to a turbo power event.

公开(公告)号：US20220376515A1

公开(公告)日：2022-11-24

申请号：US17323833

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Jagadish Singh ,  Rohit Parakkal ,  Tarakesava Reddy K ,  Arvind S ,  Arvindh Rajasekaran ,  Raghavendra R. Rao

IPC: H02J7/00 ,  H02M3/158 ,  G06F1/26

Abstract: A power architecture that uses an efficient intermediate power conversion stage between AC adaptor (and battery charger) and subsequent voltage regulators (VRs) (e.g., core VR) for processors for higher overall efficiency allowing for higher performance in a given thermal envelope and iso-system input power. Power losses from both the charger and the core VR are reduced by splitting the power as power to sustained high-power rails, and power to the rest of the platform power rails that have low residency in high-power states. The sustained high-power rails are placed under an intermediate power conversion topology which is directly powered by the adaptor. The rest of the rails along with charging of the battery are powered by the battery charger.