公开(公告)号：US11650233B2

公开(公告)日：2023-05-16

申请号：US17124358

申请日：2020-12-16

Applicant: Intel Corporation

Inventor： Neha Bhargava ,  Arvindh Rajasekaran ,  Anup Deka

IPC: G01R19/25 ,  H03K5/24 ,  G01R31/40 ,  H03K21/08 ,  H03M1/66

CPC classification number: G01R19/25 ,  G01R31/40 ,  H03K5/24 ,  H03K21/08 ,  H03M1/66

Abstract: A fast load current sensing apparatus and scheme provides instantaneous detection of peak current excursions using low silicon area and power efficient techniques. The response time for detecting signal excursions and measuring a signal (e.g., load current) is independent of resolution or precision and can be applied to high resolution telemetry. The apparatus sends out maximum current limit (FHC_limit) code at any instant the load current is detected to be more than a digital-to-analog converter (DAC) code. If the load current is less than the FHC_limit the scheme restores to a next DAC code as per a counter's next value. In case load current is more than FHC_limit, the scheme updates the DAC code to FHC_limit code and starts the counter from the FHC_limit.

公开(公告)号：US20210389353A1

公开(公告)日：2021-12-16

申请号：US17124358

申请日：2020-12-16

Applicant: Intel Corporation

Inventor： Neha Bhargava ,  Arvindh Rajasekaran ,  Anup Deka

IPC: G01R19/25 ,  H03K5/24 ,  H03K21/08 ,  G01R31/40

Abstract: A fast load current sensing apparatus and scheme provides instantaneous detection of peak current excursions using low silicon area and power efficient techniques. The response time for detecting signal excursions and measuring a signal (e.g., load current) is independent of resolution or precision and can be applied to high resolution telemetry. The apparatus sends out maximum current limit (FHC_limit) code at any instant the load current is detected to be more than a digital-to-analog converter (DAC) code. If the load current is less than the FHC_limit the scheme restores to a next DAC code as per a counter's next value. In case load current is more than FHC_limit, the scheme updates the DAC code to FHC_limit code and starts the counter from the FHC_limit.

公开(公告)号：US20220376515A1

公开(公告)日：2022-11-24

申请号：US17323833

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Jagadish Singh ,  Rohit Parakkal ,  Tarakesava Reddy K ,  Arvind S ,  Arvindh Rajasekaran ,  Raghavendra R. Rao

IPC: H02J7/00 ,  H02M3/158 ,  G06F1/26

Abstract: A power architecture that uses an efficient intermediate power conversion stage between AC adaptor (and battery charger) and subsequent voltage regulators (VRs) (e.g., core VR) for processors for higher overall efficiency allowing for higher performance in a given thermal envelope and iso-system input power. Power losses from both the charger and the core VR are reduced by splitting the power as power to sustained high-power rails, and power to the rest of the platform power rails that have low residency in high-power states. The sustained high-power rails are placed under an intermediate power conversion topology which is directly powered by the adaptor. The rest of the rails along with charging of the battery are powered by the battery charger.