公开(公告)号：US12147286B2

公开(公告)日：2024-11-19

申请号：US17129116

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Anoop Mukker ,  Romesh Trivedi ,  Suresh Nagarajan

IPC: G06F1/32 ,  G06F1/20 ,  G06F1/3221 ,  G06F1/3234

Abstract: Power management circuitry in the solid state drive monitors activity on the plurality of media channels to coordinate an active period and an idle period using credits to manage a power budget for the solid state drive. The power management circuitry to coordinate active and idle periods across components in a workload pipeline in the solid state drive for a given performance target to obtain an optimal power and thermal profile.

公开(公告)号：US10909040B2

公开(公告)日：2021-02-02

申请号：US15957650

申请日：2018-04-19

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Romesh Trivedi

IPC: G06F12/08 ,  G06F12/0871 ,  G06F12/02 ,  G06F12/0891

Abstract: A solid state drive (SSD) includes different segments of nonvolatile (NV) storage media with different access times. The NV media segment with faster access time operates as a cache for the segment with the slower access time. The SSD implements idle eviction from the cache segment to the other segment based on an idle condition of the SSD. The SSD can dynamically change application of the idle eviction based on a power management state indicated for the hardware platform. Thus, a change in power management state of the hardware platform associated with the SSD can cause the SSD to implement idle eviction differently.

公开(公告)号：US12019558B2

公开(公告)日：2024-06-25

申请号：US17122152

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Suresh Nagarajan ,  Scott Crippin ,  Sahar Khalili ,  Shankar Natarajan ,  Romesh Trivedi

IPC: G06F12/10 ,  G06F12/1009 ,  G11C16/04

CPC classification number: G06F12/1009 ,  G06F2212/657 ,  G11C16/0483

Abstract: A solid state drive with a Logical To Physical (L2P) indirection table stored in a persistent memory is provided. The L2P indirection table has a plurality of entries, each entry to store a physical block address in the block addressable memory assigned to a logical block address. The solid state drive including solid state drive controller circuitry communicatively coupled to the persistent memory and the block addressable memory. The solid state drive controller circuitry including a volatile memory to store a logical to physical address indirection table cache and circuitry to monitor the logical to physical address indirection table cache and to write dirty logical to physical entries in the logical to physical address indirection table cache to the logical to physical address indirection table in the persistent memory.

公开(公告)号：US12014081B2

公开(公告)日：2024-06-18

申请号：US17122158

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Suresh Nagarajan ,  Anoop Mukker ,  Shankar Natarajan ,  Romesh Trivedi

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Dirty Logical-to-Physical (L2P) entries in an L2P indirection table stored in a host volatile memory buffer are flushed to non-volatile memory in the solid state drive through the use of a write-back mode based on flush checkpoints. The use of write-back mode to flush dirty entries in the L2P indirection table to non-volatile memory in the solid state drive based on flush checkpoints results in an increase in the write bandwidth of the solid state drive.