公开(公告)号：US20230308193A1

公开(公告)日：2023-09-28

申请号：US18041804

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Rotem BANIN ,  Ofir DEGANI ,  Shahar GROSS ,  Run LEVINGER ,  Eytan MANN ,  Ashoke RAVI ,  Ehud RESHEF ,  Amir RUBIN ,  Eran SEGEV ,  Evgeny SHUMAKER

IPC: H04B17/14 ,  H04W56/00

CPC classification number: H04B17/14 ,  H04W56/0015

Abstract: In various aspects of this disclosure, a communication device is provided. The communication device may include a first radiohead circuit including a first transceiver chain configured to transmit a first radio frequency signal associated with a first transmission configuration and to transmit a second radio frequency signal associated with a second transmission configuration a second radiohead circuit comprising a second transceiver chain configured to receive the first radio frequency signal and the second radio frequency signal, and one or more processors configured to determine a first signal parameter associated with the first radio frequency signal received at the second transceiver chain and a second signal parameter associated with the second radio frequency signal received at the second transceiver chain, and to determine a preferred transmission configuration for the first transceiver chain by using the first signal parameter and the second signal parameter.

公开(公告)号：US20240120929A1

公开(公告)日：2024-04-11

申请号：US17956835

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Ofir DEGANI ,  Run LEVINGER ,  Ashoke RAVI

IPC: H03L7/099

CPC classification number: H03L7/0998

Abstract: The present disclosure relates to a signal generator including: a plurality of interpolators, each interpolator being configured to: receive a first input signal having a first phase, and a second input signal having a second phase; generate a plurality of interpolated signals based on a plurality of interpolations of the input signals, each interpolated signal having a respective phase based on the respective interpolation, and combine the interpolated signals to provide an output signal; the plurality of interpolators including: a first plurality of interpolators, each interpolator being configured to receive as input signals a first reference signal and a second reference signal; and a second plurality of interpolators, each interpolator being configured to receive as first input signal an output signal from an interpolator of the first plurality of interpolators and as second input signal another output signal from another interpolator of the first plurality of interpolators.

公开(公告)号：US20220094385A1

公开(公告)日：2022-03-24

申请号：US17030832

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Ofir DEGANI ,  Gil HOROVITZ ,  Evgeny SHUMAKER ,  Sergey BERSHANSKY ,  Aryeh FARBER ,  Igor GERTMAN ,  Run LEVINGER

IPC: H04B1/40

Abstract: An apparatus for generating an output oscillator signal is provided. The apparatus includes a deviation determining circuitry configured to generate a deviation signal based on a first comparison signal and a second comparison signal. Further, the apparatus includes a first oscillator configured to generate the output oscillator signal based on the deviation signal and a second oscillator signal from a second, resonator-based oscillator. The first comparison signal is based on the second oscillator signal or the output oscillator signal. The second oscillator signal has a frequency of at least 1 GHz. The second comparison signal is based on a third oscillator signal from a third oscillator. The third oscillator signal has a frequency lower than 1 GHz.

公开(公告)号：US20230307836A1

公开(公告)日：2023-09-28

申请号：US17704050

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Run LEVINGER

IPC: H01Q7/00 ,  H04B5/00

CPC classification number: H01Q7/00 ,  H04B5/0081

Abstract: A circuitry including a first S-shaped winding and a second S-shaped winding configured to form a figure-8 inductive structure; a first terminal coupled to a first end of the first S-shaped winding and a second terminal coupled to a first end of the second S-shaped winding, wherein the first terminal is configured to receive a first positive signal and the second terminal is configured to receive a first negative signal; a third terminal coupled to a second end of the first S-shaped winding and a fourth terminal coupled to a second end of the second S-shaped winding, wherein the third terminal is configured to receive a second negative signal and the fourth terminal is configured to receive a second positive signal; wherein a magnetic flux is concentrated at an intersection of the first S-shaped winding and the second S-shaped winding when a first current flows through them.

公开(公告)号：US20230299796A1

公开(公告)日：2023-09-21

申请号：US17695868

申请日：2022-03-16

Applicant: Intel Corporation

Inventor： Evgeny SHUMAKER ,  Run LEVINGER ,  Ofir DEGANI

IPC: H04B1/00 ,  H04B1/04

CPC classification number: H04B1/0014 ,  H04B1/0078 ,  H04B1/0082 ,  H04B1/0483

Abstract: A system may include a digital front end (DFE). The DFE may be configured to generate a command signal. The system may also include a sweeper. The sweeper may be configured to generate an intermediate in-phase signal, an intermediate quadrature signal, and a LO signal based on the command signal. In addition, the system may include a mixer. The mixer may be configured to generate a mixed in-phase signal based on the intermediate in-phase signal and the LO signal. The mixer may also be configured to generate a mixed quadrature signal based on the intermediate quadrature signal and the LO signal. Further, the system may include an amplifier. The amplifier may be configured to generate an in-phase signal based on the mixed in-phase signal and an amplification setting. The amplifier may also be configured to generate a quadrature signal based on the mixed quadrature signal and the amplification setting.