公开(公告)号：US20220094385A1

公开(公告)日：2022-03-24

申请号：US17030832

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Ofir DEGANI ,  Gil HOROVITZ ,  Evgeny SHUMAKER ,  Sergey BERSHANSKY ,  Aryeh FARBER ,  Igor GERTMAN ,  Run LEVINGER

IPC: H04B1/40

Abstract: An apparatus for generating an output oscillator signal is provided. The apparatus includes a deviation determining circuitry configured to generate a deviation signal based on a first comparison signal and a second comparison signal. Further, the apparatus includes a first oscillator configured to generate the output oscillator signal based on the deviation signal and a second oscillator signal from a second, resonator-based oscillator. The first comparison signal is based on the second oscillator signal or the output oscillator signal. The second oscillator signal has a frequency of at least 1 GHz. The second comparison signal is based on a third oscillator signal from a third oscillator. The third oscillator signal has a frequency lower than 1 GHz.

公开(公告)号：US20240402251A1

公开(公告)日：2024-12-05

申请号：US18326039

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Aryeh FARBER ,  Evgeny SHUMAKER ,  Samer ARRAM ,  Dana Shalala YETIV ,  Nir GERON ,  Gil HOROVITZ

IPC: G01R31/319 ,  G01R31/3193

Abstract: A mixed-signal circuit may include an analog circuit and a digital circuit coupled to the analog circuit, wherein the analog circuit is configured to, in a normal operation mode, provide an analog signal to the digital circuit, and wherein the digital circuit is configured to, in the normal operation mode, provide a digital signal to the analog circuit, the mixed-signal circuit may further include a test signal generator configured to, during a test operation mode, receive the digital signal from the digital circuit, generate a test signal based on the digital signal, and provide the test signal to the digital circuit, wherein the test signal generator is configured to generate the test signal using an emulation of the analog circuit, and wherein the mixed-signal circuit is tested based on an output of the digital circuit that is generated in response to the test signal.

公开(公告)号：US20220278690A1

公开(公告)日：2022-09-01

申请号：US17355217

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Evgeny SHUMAKER ,  Elan BANIN ,  Ofir DEGANI ,  Gil HOROVITZ

IPC: H03L7/24 ,  H03L7/099 ,  H03L7/085 ,  G04F10/00

Abstract: A TDC circuit configured to receive a reference clock (REF) signal and a signal derived from a LO; generate a plurality of digital values indicative of a measured phase difference between the signal derived from the LO and the REF signal, wherein each of the plurality of digital values are determined from a unique set of a plurality of sets of TDC measurement component quantization levels; generate a combined series of quantization levels based on a combination of the plurality of sets of TDC measurement component quantization levels; and determine a combined digital value from the combined series of quantization levels and at least one of the plurality of digital values to generate an output of the TDC circuit. The combined series of quantization levels may be generated by summing simultaneously occurring levels of each of the plurality of sets of TDC measurement component quantization levels together.