公开(公告)号：US20240345841A1

公开(公告)日：2024-10-17

申请号：US18751604

申请日：2024-06-24

Applicant: Intel Corporation

Inventor： UTKARSH Y. KAKAIYA ,  RAJESH SANKARAN ,  GILBERT NEIGER ,  PHILIP LANTZ ,  SANJAY K. KUMAR

IPC: G06F9/34 ,  G06F9/30 ,  G06F12/109

CPC classification number: G06F9/34 ,  G06F9/30098 ,  G06F12/109 ,  G06F2212/657

Abstract: In one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (PASID) table; and an execution circuit coupled to the first configuration register. The execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a PASID table handle from the command data, access a first entry of the PASID table using the pointer from the first configuration register and the PASID table handle to obtain a PASID value, insert the PASID value into the command data, and send the command data to a device coupled to the processor. Other embodiments are described and claimed.

公开(公告)号：US20230023329A1

公开(公告)日：2023-01-26

申请号：US17891180

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： UTKARSH Y. KAKAIYA ,  RAJESH SANKARAN ,  GILBERT NEIGER ,  PHILIP LANTZ ,  SANJAY K. KUMAR

IPC: G06F9/34 ,  G06F9/30 ,  G06F12/109

Abstract: In one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (PASID) table; and an execution circuit coupled to the first configuration register. The execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a PASID table handle from the command data, access a first entry of the PASID table using the pointer from the first configuration register and the PASID table handle to obtain a PASID value, insert the PASID value into the command data, and send the command data to a device coupled to the processor. Other embodiments are described and claimed.

公开(公告)号：US20200319913A1

公开(公告)日：2020-10-08

申请号：US16909068

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： SANJAY K. KUMAR ,  RAJESH SANKARAN ,  UTKARSH Y. KAKAIYA ,  PRATIK M. MAROLIA

IPC: G06F9/455 ,  G06F12/10

Abstract: In one embodiment, an apparatus includes an input/output virtualization (IOV) device comprising: at least one function circuit to be shared by a plurality of virtual machines (VMs); and a plurality of assignable device interfaces (ADIs) coupled to the at least one function circuit, wherein each of the plurality of ADIs is to be associated with one of the plurality of VMs and comprises a first process address space identifier (PASID) field to store a first PASID to identify a descriptor queue stored in a host address space and a second PASID field to store a second PASID to identify a data buffer located in a VM address space. Other embodiments are described and claimed.

公开(公告)号：US20210406055A1

公开(公告)日：2021-12-30

申请号：US16911445

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： UTKARSH Y. KAKAIYA ,  SANJAY K. KUMAR ,  PHILIP LANTZ ,  GILBERT NEIGER ,  RAJESH SANKARAN ,  VEDVYAS SHANBHOGUE

IPC: G06F9/455 ,  G06F9/30 ,  G06F9/50 ,  G06F9/54

Abstract: In one embodiment, a processor comprises: a first configuration register to store quality of service (QoS) information for a process address space identifier (PASID) value associated with a first process; and an execution circuit coupled to the first configuration register, where the execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, insert the QoS information and the PASID value into the command data, and send a request comprising the command data to a device coupled to the processor, to enable the device to use the QoS information of a plurality of requests to manage sharing between a plurality of processes. Other embodiments are described and claimed.

公开(公告)号：US20210406022A1

公开(公告)日：2021-12-30

申请号：US16911441

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： UTKARSH Y. KAKAIYA ,  RAJESH SANKARAN ,  GILBERT NEIGER ,  PHILIP LANTZ ,  SANJAY K. KUMAR

IPC: G06F9/34 ,  G06F9/30

Abstract: In one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (PASID) table; and an execution circuit coupled to the first configuration register. The execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a PASID table handle from the command data, access a first entry of the PASID table using the pointer from the first configuration register and the PASID table handle to obtain a PASID value, insert the PASID value into the command data, and send the command data to a device coupled to the processor. Other embodiments are described and claimed.

公开(公告)号：US20210342182A1

公开(公告)日：2021-11-04

申请号：US16909084

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： SANJAY K. KUMAR ,  PHILIP LANTZ ,  RAJESH SANKARAN ,  NARAYAN RANGANATHAN ,  SAURABH GAYEN ,  DAVID A. KOUFATY ,  UTKARSH Y. KAKAIYA

IPC: G06F9/48 ,  G06F9/34 ,  G06F9/455 ,  G06F12/109 ,  G06F12/14

Abstract: In one embodiment, a data mover accelerator is to receive, from a first agent having a first address space and a first process address space identifier (PASID) to identify the first address space, a first job descriptor comprising a second PASID selector to specify a second PASID to identify a second address space. In response to the first job descriptor, the data mover accelerator is to securely access the first address space and the second address space. Other embodiments are described and claimed.