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    MEMORY PROTECTION KEY ARCHITECTURE WITH INDEPENDENT USER AND SUPERVISOR DOMAINS
    1.
    发明申请
    MEMORY PROTECTION KEY ARCHITECTURE WITH INDEPENDENT USER AND SUPERVISOR DOMAINS 审中-公开
    具有独立用户和监管域的记忆保护关键体系结构

    公开(公告)号：US20160110298A1

    公开(公告)日：2016-04-21

    申请号：US14519648

    申请日：2014-10-21

    Applicant: Intel Corporation

    Inventor： DAVID A. KOUFATY ,  GILBERT NEIGER ,  RAJESH M. SANKARAN ,  ANDREW V. ANDERSON ,  SUBRAMANYA R. DULLOOR ,  WERNER HAAS ,  JOSEPH NUZMAN

    IPC: G06F12/14 ,  G06F21/62

    CPC classification number: G06F12/1466 ,  G06F21/52 ,  G06F2212/1052

    Abstract: A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a storage unit to store a page table entry including one or more identifiers of memory frames, a protection key, and an access mode bit indicating whether the one or more memory frames are accessible according to a user mode or according to a supervisor mode, a first permission register including a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the user mode, and a second permission register storing a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the supervisor mode.

    Abstract translation: 处理系统包括执行任务的处理核心和耦合到核心的存储器管理单元。 存储器管理单元包括：存储单元，用于存储包括存储器帧的一个或多个标识符的页表项，保护密钥和指示一个或多个存储器帧是否可根据用户模式访问的访问模式位，或者根据 管理员模式，包括多个字段的第一允许寄存器，每个字段包括反映用户模式下的一组存储器访问许可的位数，以及存储多个字段的第二许可寄存器，每个字段包括一组 在管理员模式下反映一组内存访问权限的位。

    TECHNIQUES FOR MANAGING ACCESS TO HARDWARE ACCELERATOR MEMORY
    3.
    发明申请
    TECHNIQUES FOR MANAGING ACCESS TO HARDWARE ACCELERATOR MEMORY 审中-公开

    公开(公告)号：US20190018806A1

    公开(公告)日：2019-01-17

    申请号：US15650112

    申请日：2017-07-14

    Applicant: INTEL CORPORATION

    Inventor： DAVID A. KOUFATY ,  RAJESH M. SANKARAN ,  STEPHEN R. VAN DOREN

    IPC: G06F13/16 ,  G06F15/78 ,  G06F9/46 ,  G06F3/06 ,  G06F21/71 ,  G06F12/10

    Abstract: Techniques and apparatus to manage access to accelerator-attached memory are described. In one embodiment, an apparatus to provide coherence bias for accessing accelerator memory may include at least one processor, a logic device communicatively coupled to the at least one processor, a logic device memory communicatively coupled to the logic device, and logic, at least a portion comprised in hardware, the logic to receive a request to access the logic device memory from the logic device, determine a bias mode associated with the request, and provide the logic device with access to the logic device memory via a device bias pathway responsive to the bias mode being a device bias mode. Other embodiments are described and claimed.

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